Understanding dual-gate polymer field-effect transistors

Since the first report that the use of regioregular conjugated polymer semiconductors results in significantly improved device performance in field-effect transistors (FETs), research into polymer FETs such as novel material development, fabrication processes optimization and device architectures employment has been focused [1-2]. One of such attempts is dual-gate configuration based polymer FETs. In a dual-gate device, the semiconductor active layer is sandwiched between two separate dielectrics and carrier concentration or the channel conductivity can be effectively controlled through the voltages applied independently to the top and bottom gate electrodes. Dual-gate devices have been investigated to obtain improved performance such as higher on-current, increased on-off current ratio and decreased threshold voltage [3-4].