A high performance scan flip-flop design for serial and mixed mode scan test

Over the years, serial scan design has became the defacto Design for Testability (DFT) technique. The ease of testing and high test coverage has made it to gain wide spread industrial acceptance. However, there are associated penalties with serial scan. These penalties include performance degradation, test data volume, test application time, and test power dissipation. The performance overhead of scan design is due to the scan multiplexers added to the inputs of every flip-flop. In today's very high speed designs with minimum possible combinational depth, the performance degradation caused by scan multiplexer has became magnified. Hence to maintain the circuit performance the timing overhead of scan design must be addressed. In this paper we propose a new scan flip-flop design that eliminates the performance overhead of serial scan. The proposed design removes the scan multiplexer off the functional path. The proposed design can help in improving the functional frequency of performance critical designs. Furthermore, the proposed design can be used as a common scan flip-flop in mixed mode scan test wherein it can be used as a serial scan cell as well as random access scan RAS) cell.