Development of CMOS-process-compatible interconnect technology for 3D-stacking of NAND flash memory chips

Abstract

Through-silicon-via (TSV) technology has been demonstrated to be capable of being applied into many microelectronics products, e.g., CMOS image sensor (CIS), DRAM, flash memory, 3D-MEMS, RF-SiP, logic-SiP, LED, etc. However, new IC design is needed to implement the TSV interconnect into a chip and the specific TSV line is required for TSV fabrication, the facts of long time needed for new IC design qualification and implementation plus big facility investment required for setting-up a full functional TSV line result in high manufacturing cost which further hinders the applications of TSV interconnect technology into many products, e.g., DRAM and flash memory. In this paper, a new TSV-based interconnect technology, named under-pad interconnect (UPI), has been developed for 3D-stacking of NAND flash memory chips using existing CMOS-compatible processes. The basic idea is to use the existing wire-bonding (WB) based NAND flash memory wafer to fabricate blind-via interconnect under bond pad from the backside of a wafer, followed by stacking the chips with UPIs onto the substrate to build a 3D-module. The details of the fabrication process development and the NAND flash memory 3D-stacking methodology will be reviewed and discussed.