Pub Date : 2010-06-01DOI: 10.1109/ECTC.2010.5490809
M. Doyle, J. Bartley, R. Ericson, M. Bailey, P. Germann, G. Zettles
Current industry trends, combined with present cost pressures shall force signal integrity engineers to revisit traditional “rules of thumb” such that additional bandwidth can be obtained from conventional (standard) packaging materials and methodologies. In this paper, the authors assert that some current design practices prematurely cap the useful bandwidth of current technology, and unnecessarily lead designers to ask material scientists to solve our bandwidth concerns. Every facet of the electronics industry is subject to cost pressures. Opposite these financial constraints is the continuing drive to improve performance. Every new product must evaluate the business case for the use or inclusion of a new technology, more expensive component, or increase in power. The larger design community tends to move together into and out of technology “nodes” as they become more feasible and cost effective. Whether or not a particular technology is effective at meeting the design and business goals is a function of what other technologies and consequences are traded off in order to use it. This paper examines the conventional wisdom of some common practices, in light of an attempt to forego the use of advanced packaging technologies while extending the practical life of lower-cost techniques to signaling interfaces with higher frequency content.
{"title":"Extending lower-cost packaging technology into next generation signaling: Techniques and considerations","authors":"M. Doyle, J. Bartley, R. Ericson, M. Bailey, P. Germann, G. Zettles","doi":"10.1109/ECTC.2010.5490809","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490809","url":null,"abstract":"Current industry trends, combined with present cost pressures shall force signal integrity engineers to revisit traditional “rules of thumb” such that additional bandwidth can be obtained from conventional (standard) packaging materials and methodologies. In this paper, the authors assert that some current design practices prematurely cap the useful bandwidth of current technology, and unnecessarily lead designers to ask material scientists to solve our bandwidth concerns. Every facet of the electronics industry is subject to cost pressures. Opposite these financial constraints is the continuing drive to improve performance. Every new product must evaluate the business case for the use or inclusion of a new technology, more expensive component, or increase in power. The larger design community tends to move together into and out of technology “nodes” as they become more feasible and cost effective. Whether or not a particular technology is effective at meeting the design and business goals is a function of what other technologies and consequences are traded off in order to use it. This paper examines the conventional wisdom of some common practices, in light of an attempt to forego the use of advanced packaging technologies while extending the practical life of lower-cost techniques to signaling interfaces with higher frequency content.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116937427","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-01DOI: 10.1109/ECTC.2010.5490731
D. Malta, C. Gregory, D. Temple, T. Knutson, Chen Wang, T. Richardson, Yun Zhang, R. Rhoades
The fabrication of through-silicon vias (TSVs) is a major component in the development of three-dimensional (3D) integration technology and advanced 3D packaging approaches. The large diameter and length of TSVs, as compared to traditional interconnects, create some unique process challenges. Via plating and chemical-mechanical polishing (CMP) processes used in standard copper interconnect technology are generally not suitable for TSV fabrication. Therefore, efforts are being made to develop such processes specifically for TSV technology. This paper will describe the development of a void-free Cu electroplating process for TSV filling, along with CMP processing to remove the overburden layer and expose the Cu-filled vias for subsequent metallization. The focus of the paper will be the integration of the TSV plating and CMP processes, with discussion regarding observed integration challenges and their solutions. First, a Cu electroplating process was developed for defect-free, bottom-up filling of silicon vias from 20–200µm in diameter and 150–375µm deep, with aspect ratios from 1:1 to 8:1. Next, CMP tests were conducted using Cu-filled silicon vias of 50µm diameter and 150µm depth, designed for use in a MEMS wafer-level packaging application. These tests indicated that plating nonuniformity and Cu mound defects over filled vias caused significant CMP process issues. The plating process was then modified to eliminate these problems in the Cu films, resulting in improved CMP uniformity and reduced polishing time.
{"title":"Integrated process for defect-free copper plating and chemical-mechanical polishing of through-silicon vias for 3D interconnects","authors":"D. Malta, C. Gregory, D. Temple, T. Knutson, Chen Wang, T. Richardson, Yun Zhang, R. Rhoades","doi":"10.1109/ECTC.2010.5490731","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490731","url":null,"abstract":"The fabrication of through-silicon vias (TSVs) is a major component in the development of three-dimensional (3D) integration technology and advanced 3D packaging approaches. The large diameter and length of TSVs, as compared to traditional interconnects, create some unique process challenges. Via plating and chemical-mechanical polishing (CMP) processes used in standard copper interconnect technology are generally not suitable for TSV fabrication. Therefore, efforts are being made to develop such processes specifically for TSV technology. This paper will describe the development of a void-free Cu electroplating process for TSV filling, along with CMP processing to remove the overburden layer and expose the Cu-filled vias for subsequent metallization. The focus of the paper will be the integration of the TSV plating and CMP processes, with discussion regarding observed integration challenges and their solutions. First, a Cu electroplating process was developed for defect-free, bottom-up filling of silicon vias from 20–200µm in diameter and 150–375µm deep, with aspect ratios from 1:1 to 8:1. Next, CMP tests were conducted using Cu-filled silicon vias of 50µm diameter and 150µm depth, designed for use in a MEMS wafer-level packaging application. These tests indicated that plating nonuniformity and Cu mound defects over filled vias caused significant CMP process issues. The plating process was then modified to eliminate these problems in the Cu films, resulting in improved CMP uniformity and reduced polishing time.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124765886","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-01DOI: 10.1109/ECTC.2010.5490754
A. Yu, C. Premachandran, R. Nagarajan, C.W. Kyoung, Lam Quynh Trang, Rakesh Kumar, L. Lim, J. H. Han, Yap Guan Jie, P. Damaruganath
This paper discusses wafer level vacuum sealing technology with evaporated AuSn solder for a microelectromechanical systems (MEMS) resonator without getter material. The MEMS resonator is fabricated and characterized in a vacuum chamber. Relationship between the Q-factor of the MEMS resonator and the vacuum level is established and used as a reference for later vacuum level calibration. Wafer bonding using evaporated AuSn solder is performed in an EVG wafer bonder. With optimized bonding conditions, the achieved shear strength is higher than 59 MPa and uniform cross-section of the bonding ring has been achieved. The calculated He leakage rate is between 10−13 atm cc/s and 10−14 atm cc/s. By comparing the measured Q-factor of packaged resonator with the reference curve, the corresponding vacuum level is 0.2 Torr. Reliability tests results show that shear strength decreases for 7% and still high enough for real application. The vacuum level after reliability tests is comparable to that of long term vacuum level.
{"title":"Design, process integration and characterization of wafer level vacuum packaging for MEMS resonator","authors":"A. Yu, C. Premachandran, R. Nagarajan, C.W. Kyoung, Lam Quynh Trang, Rakesh Kumar, L. Lim, J. H. Han, Yap Guan Jie, P. Damaruganath","doi":"10.1109/ECTC.2010.5490754","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490754","url":null,"abstract":"This paper discusses wafer level vacuum sealing technology with evaporated AuSn solder for a microelectromechanical systems (MEMS) resonator without getter material. The MEMS resonator is fabricated and characterized in a vacuum chamber. Relationship between the Q-factor of the MEMS resonator and the vacuum level is established and used as a reference for later vacuum level calibration. Wafer bonding using evaporated AuSn solder is performed in an EVG wafer bonder. With optimized bonding conditions, the achieved shear strength is higher than 59 MPa and uniform cross-section of the bonding ring has been achieved. The calculated He leakage rate is between 10−13 atm cc/s and 10−14 atm cc/s. By comparing the measured Q-factor of packaged resonator with the reference curve, the corresponding vacuum level is 0.2 Torr. Reliability tests results show that shear strength decreases for 7% and still high enough for real application. The vacuum level after reliability tests is comparable to that of long term vacuum level.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125839240","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-01DOI: 10.1109/ECTC.2010.5490791
Jeremias P. Libres, J. C. Arroyo
The demand for die to package interconnects free of Pb in the next generation flip chip packages requires a flux and underfill solution that meets package reliability requirements. Bump cracks and bump deformation were observed during temperature cycling on large body, full Pb-free ceramic flip chip BGA packages during initial package development. The phenomenon is considered unique in terms of its nature and failure mechanism. Traditional bump crack issues are concentrated at or near the silicon and underfill interfaces. In this case, cracks occurred within the bulk solder away from either silicon or substrate interface. Failed bumps also showed severe deformation. In addition, morphology differences in the underfill material surrounding the affected bumps provided important clues as to the nature of the failure mechanism. An extensive investigation to understand the root cause of the unique bump crack issue in the bulk solder, which covered both process and material-related factors, resulted in a clear understanding of the failure mechanism and the implementation of an effective solution to the problem. This manuscript describes the relationship of the flux residue-underfill interaction, the localized change in underfill properties due to the flux residues, and eventually the impact of this change on the bump integrity during package stressing. These findings made it possible to establish a good flux-underfill selection methodology to achieve a robust Pb-free package solution that is being implemented in next generation flip chip products.
{"title":"Investigation of bump crack and deformation on Pb-free flip chip packages","authors":"Jeremias P. Libres, J. C. Arroyo","doi":"10.1109/ECTC.2010.5490791","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490791","url":null,"abstract":"The demand for die to package interconnects free of Pb in the next generation flip chip packages requires a flux and underfill solution that meets package reliability requirements. Bump cracks and bump deformation were observed during temperature cycling on large body, full Pb-free ceramic flip chip BGA packages during initial package development. The phenomenon is considered unique in terms of its nature and failure mechanism. Traditional bump crack issues are concentrated at or near the silicon and underfill interfaces. In this case, cracks occurred within the bulk solder away from either silicon or substrate interface. Failed bumps also showed severe deformation. In addition, morphology differences in the underfill material surrounding the affected bumps provided important clues as to the nature of the failure mechanism. An extensive investigation to understand the root cause of the unique bump crack issue in the bulk solder, which covered both process and material-related factors, resulted in a clear understanding of the failure mechanism and the implementation of an effective solution to the problem. This manuscript describes the relationship of the flux residue-underfill interaction, the localized change in underfill properties due to the flux residues, and eventually the impact of this change on the bump integrity during package stressing. These findings made it possible to establish a good flux-underfill selection methodology to achieve a robust Pb-free package solution that is being implemented in next generation flip chip products.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"159 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114911941","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-01DOI: 10.1109/ECTC.2010.5490775
G. Ponchak, J. Jordan, M. Scardelletti
In this paper, we present an analysis of inductors on an Alumina substrate over the temperature range of 25 to 475° C. Five sets of inductors, each set consisting of a 1.5, 2.5, 3.5, and a 4.5 turn inductor with different line width and spacing, were measured on a high temperature probe station from 10 MHz to 30 GHz. From these measured characteristics, it is shown that the inductance is nearly independent of temperature for low frequencies compared to the self resonant frequency, the parasitic capacitances are independent of temperature, and the resistance varies nearly linearly with temperature. These characteristics result in the self resonant frequency decreasing by only a few percent as the temperature is increased from 25 to 475° C, but the maximum quality factor decreases by a factor of 2 to 3. These observations based on measured data are confirmed through 2D simulations using Sonnet software.
{"title":"Temperature dependence of thin film spiral inductors on Alumina over a temperature range of 25 to 475° C","authors":"G. Ponchak, J. Jordan, M. Scardelletti","doi":"10.1109/ECTC.2010.5490775","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490775","url":null,"abstract":"In this paper, we present an analysis of inductors on an Alumina substrate over the temperature range of 25 to 475° C. Five sets of inductors, each set consisting of a 1.5, 2.5, 3.5, and a 4.5 turn inductor with different line width and spacing, were measured on a high temperature probe station from 10 MHz to 30 GHz. From these measured characteristics, it is shown that the inductance is nearly independent of temperature for low frequencies compared to the self resonant frequency, the parasitic capacitances are independent of temperature, and the resistance varies nearly linearly with temperature. These characteristics result in the self resonant frequency decreasing by only a few percent as the temperature is increased from 25 to 475° C, but the maximum quality factor decreases by a factor of 2 to 3. These observations based on measured data are confirmed through 2D simulations using Sonnet software.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115536263","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-01DOI: 10.1109/ECTC.2010.5490659
G. Orecchini, R. Zhang, J. Agar, D. Staiculescu, M. Tentzeris, L. Roselli, C. Wong
Embedded paper electronics is a promising solution for the future of electronics, and thus the goal for this paper is to show the pathway toward achieving inkjet solutions for the realization of complex circuitry on the cheapest synthetic material made by humankind: PAPER. A direct write technology, inkjet printing transfers the designed pattern directly to the substrate. Inkjet technologies have gained a lot of ground as a more accurate and economic fabrication method than traditional lithography. The challenge of this work is to identify the right materials and to show the printability of all the building blocks of an organic field-effect transistor (OTFT). For the semiconductor, a highly soluble pentacene precursor, 13,6-N-Sulfinylacetamidopentacene, is proposed. Anisole, a high boiling point solvent is chosen to insure proper jetting of the solution. The solution jets well and it has to be used right after preparation as its printability degrades with time. For the gate dielectric, two solutions are proposed: (i) using the paper itself as an insulator and print a bottom gate device on both sides of a double sided glossy paper, (ii) a pentacene impurity, of 6,13-pentacenequinone (PQ), in a top gate configuration, which may improve the device mobility by reducing the scattering sites at the semiconductor-dielectric interface. For the electrodes, a printable nano-particle based silver ink has to be modified to match the work function with pentacene, or replaced with an alternate printable material like Carbon Nanotubes (CNTs). Preliminary electrical testing of the pentacene film printed directly on paper shows good conduction properties for a 25 µm channel length. Further improvement of the pentacene film performance is proposed. This work establishes the foundation for the first fully printed OTFT on paper.
嵌入式纸质电子产品是未来电子产品的一个很有前途的解决方案，因此本文的目标是展示实现喷墨解决方案的途径，以实现人类最便宜的合成材料:纸上的复杂电路。一种直接写入技术，喷墨印刷将设计的图案直接转移到承印物上。喷墨技术作为一种比传统光刻技术更精确、更经济的制造方法而获得了广泛的应用。这项工作的挑战在于确定合适的材料，并展示有机场效应晶体管(OTFT)的所有构建块的可印刷性。对于半导体，提出了一种高可溶性的并戊烯前体13,6- n -亚砜酰乙酰胺对戊烯。苯甲醚，一种高沸点的溶剂选择，以确保适当的喷射溶液。溶液喷射良好，它必须在制备后立即使用，因为它的印刷性随着时间的推移而降低。对于栅极介质，提出了两种解决方案:(i)使用纸张本身作为绝缘体，在双面光面纸的两侧打印底部栅极器件;(ii)在顶部栅极配置中添加6,13-pentacenequinone (PQ)的并五苯杂质，通过减少半导体-介电界面上的散射位，可以提高器件的迁移率。对于电极，基于纳米颗粒的可打印银墨水必须被修改以匹配并五苯的功函数，或者用碳纳米管(CNTs)等替代可打印材料代替。直接印刷在纸上的并五苯薄膜的初步电学测试表明，在25 μ m通道长度下，该薄膜具有良好的导电性能。提出了进一步改进并五苯薄膜性能的方法。这项工作为第一个完全印刷在纸上的OTFT奠定了基础。
{"title":"Inkjet printed organic transistors for sustainable electronics","authors":"G. Orecchini, R. Zhang, J. Agar, D. Staiculescu, M. Tentzeris, L. Roselli, C. Wong","doi":"10.1109/ECTC.2010.5490659","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490659","url":null,"abstract":"Embedded paper electronics is a promising solution for the future of electronics, and thus the goal for this paper is to show the pathway toward achieving inkjet solutions for the realization of complex circuitry on the cheapest synthetic material made by humankind: PAPER. A direct write technology, inkjet printing transfers the designed pattern directly to the substrate. Inkjet technologies have gained a lot of ground as a more accurate and economic fabrication method than traditional lithography. The challenge of this work is to identify the right materials and to show the printability of all the building blocks of an organic field-effect transistor (OTFT). For the semiconductor, a highly soluble pentacene precursor, 13,6-N-Sulfinylacetamidopentacene, is proposed. Anisole, a high boiling point solvent is chosen to insure proper jetting of the solution. The solution jets well and it has to be used right after preparation as its printability degrades with time. For the gate dielectric, two solutions are proposed: (i) using the paper itself as an insulator and print a bottom gate device on both sides of a double sided glossy paper, (ii) a pentacene impurity, of 6,13-pentacenequinone (PQ), in a top gate configuration, which may improve the device mobility by reducing the scattering sites at the semiconductor-dielectric interface. For the electrodes, a printable nano-particle based silver ink has to be modified to match the work function with pentacene, or replaced with an alternate printable material like Carbon Nanotubes (CNTs). Preliminary electrical testing of the pentacene film printed directly on paper shows good conduction properties for a 25 µm channel length. Further improvement of the pentacene film performance is proposed. This work establishes the foundation for the first fully printed OTFT on paper.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115568740","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-01DOI: 10.1109/ECTC.2010.5490967
M. Amagai, Yutaka Suzuki
Package warpage is a primary concern in a package-on-package. To enhance the accuracy of modeling prediction, viscoelastic parameters, the change of material properties after injection mold cure (IMC) and post mold cure (PMC) temperature and it's time, and cure shrinkage were studied with a dynamic modulus analysis (DMA) and a thermal mechanical analysis (TMA) for a mold compound. A nano-indentation tool was used to characterize a viscoelasticity of underfill material. Material properties obtained from the TMA, DMA and nano-indentation tools were introduced to finite-element-based models. The validation of models was verified with a shadow moiré for package warpage.
{"title":"A study of package warpage for package on package (PoP)","authors":"M. Amagai, Yutaka Suzuki","doi":"10.1109/ECTC.2010.5490967","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490967","url":null,"abstract":"Package warpage is a primary concern in a package-on-package. To enhance the accuracy of modeling prediction, viscoelastic parameters, the change of material properties after injection mold cure (IMC) and post mold cure (PMC) temperature and it's time, and cure shrinkage were studied with a dynamic modulus analysis (DMA) and a thermal mechanical analysis (TMA) for a mold compound. A nano-indentation tool was used to characterize a viscoelasticity of underfill material. Material properties obtained from the TMA, DMA and nano-indentation tools were introduced to finite-element-based models. The validation of models was verified with a shadow moiré for package warpage.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"238 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116390499","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-01DOI: 10.1109/ECTC.2010.5490723
D. Cavasin
As Pb-free packaging technologies evolve, increased emphasis has been placed on the development of robust mechanical and metallurgical solutions. A number of different component and PCB surface finish options are now widely available, as are several different BGA solder ball alloys. Similarly, various different Pb-free C4 bumping alloys are being introduced, compounding the need for clear understanding of how the resulting interconnect systems stand up to the normal rigors of end-user applications. This paper focuses on the component-level reliability and metallurgical evolution of the C4 (flip chip) and BGA interconnect systems formed by the combination of commonly specified surface finishes and BGA solder alloys. The two surface finishes selected were electroless Ni/electroless Pd/immersion Au (ENEPIG), and immersion Sn (IT). The selected BGA alloys were Sn-3Ag-0.5Cu (SAC305) and Sn-3.5Ag. All four of these alloy/pad finish combinations were found to pass the various industry-standard (JEDEC) reliability stress tests without any failures, as measured through open/short testing and CSAM analyses of the packages. However, significant differences in microstructural evolution of the solder/substrate interfaces were observed.
{"title":"An investigation of reliability and solder joint microstructure evolution of select Pb-free FCBGA pad finish and solder ball alloy combinations","authors":"D. Cavasin","doi":"10.1109/ECTC.2010.5490723","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490723","url":null,"abstract":"As Pb-free packaging technologies evolve, increased emphasis has been placed on the development of robust mechanical and metallurgical solutions. A number of different component and PCB surface finish options are now widely available, as are several different BGA solder ball alloys. Similarly, various different Pb-free C4 bumping alloys are being introduced, compounding the need for clear understanding of how the resulting interconnect systems stand up to the normal rigors of end-user applications. This paper focuses on the component-level reliability and metallurgical evolution of the C4 (flip chip) and BGA interconnect systems formed by the combination of commonly specified surface finishes and BGA solder alloys. The two surface finishes selected were electroless Ni/electroless Pd/immersion Au (ENEPIG), and immersion Sn (IT). The selected BGA alloys were Sn-3Ag-0.5Cu (SAC305) and Sn-3.5Ag. All four of these alloy/pad finish combinations were found to pass the various industry-standard (JEDEC) reliability stress tests without any failures, as measured through open/short testing and CSAM analyses of the packages. However, significant differences in microstructural evolution of the solder/substrate interfaces were observed.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114046012","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-01DOI: 10.1109/ECTC.2010.5490929
Chaoran Yang, F. Song, S. Lee, K. Newman
Pad cratering is one of the dominant failure modes that occur in various board level reliability tests, especially under the dynamic loading. In recent years, the increasing propensity of pad cratering due to the implementation of the lead-free technology calls for the necessity of re-assessment of PWB qualification related to the pad cratering resistance. The objective of the present study is to establish a test method for evaluating the pad cratering resistance of PWB and studying the PWB degradation mechanism subject to different high temperature conditions. Three kinds of PWB with different resin systems were investigated, including one phenolic-cured system board and two dicy-cured system boards. Tg and Td of the selected PWBs were characterized using TMA and TGA. The detailed cold ball pull test procedure is presented and different pull jaws with/without standoff are evaluated in this paper. The effects of multiple reflows, thermal aging and temperature cycling on the pad cratering resistance of PWBs are discussed as well.
{"title":"Comparative study of PWB pad cratering subject to reflow soldering and thermal impact","authors":"Chaoran Yang, F. Song, S. Lee, K. Newman","doi":"10.1109/ECTC.2010.5490929","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490929","url":null,"abstract":"Pad cratering is one of the dominant failure modes that occur in various board level reliability tests, especially under the dynamic loading. In recent years, the increasing propensity of pad cratering due to the implementation of the lead-free technology calls for the necessity of re-assessment of PWB qualification related to the pad cratering resistance. The objective of the present study is to establish a test method for evaluating the pad cratering resistance of PWB and studying the PWB degradation mechanism subject to different high temperature conditions. Three kinds of PWB with different resin systems were investigated, including one phenolic-cured system board and two dicy-cured system boards. Tg and Td of the selected PWBs were characterized using TMA and TGA. The detailed cold ball pull test procedure is presented and different pull jaws with/without standoff are evaluated in this paper. The effects of multiple reflows, thermal aging and temperature cycling on the pad cratering resistance of PWBs are discussed as well.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114283870","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-01DOI: 10.1109/ECTC.2010.5490928
Huili Xu, W. Bang, Hongtao Ma, Tae-Kyu Lee, K. Liu, C. Kim
This paper reports the experimental and theoretical exploration of the fracture mechanism active in BGA lead-free solder assemblies under high speed shear fatigue test conditions. Our investigation finds that, contrary to common assumption, the crack growth in shear fatigue is not governed by shear stress but more by crack opening stress. Our theoretical analysis indicates that fracture by crack opening mode prevails because non-uniformity in the shear deformation of solder joint creates a body rotation which results in crack opening stress rather than shear. While the crack growth in shear fatigue is found to vary sensitively with variation in the mechanical constraints on the assembly, such as solder shape and elastic modulus of the chip mold, it is also sensitive to variation in solder microstructure. This, the sensitivity to the assembly constraints and solder microstructure, makes it ideal in investigating fatigue properties of solder joints as well as identifying the structural and microstructural features responsible for reliability failure.
{"title":"Fracture mechanics of lead-free solder joints under cyclic shear load","authors":"Huili Xu, W. Bang, Hongtao Ma, Tae-Kyu Lee, K. Liu, C. Kim","doi":"10.1109/ECTC.2010.5490928","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490928","url":null,"abstract":"This paper reports the experimental and theoretical exploration of the fracture mechanism active in BGA lead-free solder assemblies under high speed shear fatigue test conditions. Our investigation finds that, contrary to common assumption, the crack growth in shear fatigue is not governed by shear stress but more by crack opening stress. Our theoretical analysis indicates that fracture by crack opening mode prevails because non-uniformity in the shear deformation of solder joint creates a body rotation which results in crack opening stress rather than shear. While the crack growth in shear fatigue is found to vary sensitively with variation in the mechanical constraints on the assembly, such as solder shape and elastic modulus of the chip mold, it is also sensitive to variation in solder microstructure. This, the sensitivity to the assembly constraints and solder microstructure, makes it ideal in investigating fatigue properties of solder joints as well as identifying the structural and microstructural features responsible for reliability failure.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114487792","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：