{"title":"Low-power digital PLL with one cycle frequency lock-in time and large frequency-multiplication factor for advanced power management","authors":"R. Fried, Z. Azmanov","doi":"10.1109/ICECS.1996.584629","DOIUrl":null,"url":null,"abstract":"A low-power Digital PLL (DPLL) with +/-100 ps jitter and one cycle frequency lock-in time is presented. It is used to generate clock frequencies up to 100 MHz using a 32,768 Hz reference clock. The DPLL is especially designed for advanced power management and performance enhancement, both at a chip level and system level.","PeriodicalId":402369,"journal":{"name":"Proceedings of Third International Conference on Electronics, Circuits, and Systems","volume":"128 4","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1996-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of Third International Conference on Electronics, Circuits, and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICECS.1996.584629","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 6
Abstract
A low-power Digital PLL (DPLL) with +/-100 ps jitter and one cycle frequency lock-in time is presented. It is used to generate clock frequencies up to 100 MHz using a 32,768 Hz reference clock. The DPLL is especially designed for advanced power management and performance enhancement, both at a chip level and system level.
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