Pub Date : 1996-10-13DOI: 10.1109/ICECS.1996.582638
B.D.E. Smith, J. McCanny
The design and VLSI implementation of two key components of the class-IV partial response maximum likelihood channel (PR-IV), the adaptive filter and the Viterbi decoder are described. These blocks are implemented using parameterised VHDL modules, from a library of common digital signal processing (DSP) and arithmetic functions. Design studies, based on 0.6 micron 3.3 V standard cell processes, indicate that worst case sampling rates of 49 mega-samples per second are achievable for this system, with proportionally high sampling rates for full custom designs and smaller dimension processes. Significant increases in the sampling rate, from 49 MHz to approximately 180 MHz, can be achieved by operating four filter modules in parallel, and this implementation has 50% lower power consumption than a pipelined filter operating at the same speed.
{"title":"Synthesisable high performance adaptive equaliser and Viterbi decoder for the Class-IV PRML channel","authors":"B.D.E. Smith, J. McCanny","doi":"10.1109/ICECS.1996.582638","DOIUrl":"https://doi.org/10.1109/ICECS.1996.582638","url":null,"abstract":"The design and VLSI implementation of two key components of the class-IV partial response maximum likelihood channel (PR-IV), the adaptive filter and the Viterbi decoder are described. These blocks are implemented using parameterised VHDL modules, from a library of common digital signal processing (DSP) and arithmetic functions. Design studies, based on 0.6 micron 3.3 V standard cell processes, indicate that worst case sampling rates of 49 mega-samples per second are achievable for this system, with proportionally high sampling rates for full custom designs and smaller dimension processes. Significant increases in the sampling rate, from 49 MHz to approximately 180 MHz, can be achieved by operating four filter modules in parallel, and this implementation has 50% lower power consumption than a pipelined filter operating at the same speed.","PeriodicalId":402369,"journal":{"name":"Proceedings of Third International Conference on Electronics, Circuits, and Systems","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116758574","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-10-13DOI: 10.1109/ICECS.1996.582687
A. Al-Saqer, Nabil I. Khachab, J. G. Varghese
Two second order filter architectures are presented with applications to double and single ended multiple input amplifier configurations. These circuits can be configured to perform BP, HP, LP and notch filter functions. The Gm tunability of the fully-complementary, Composite Folded Cascode (CFC) based amplifier test structures is achieved by a MOSR scheme with center-frequency variations in the upper Megahertz range, using power supplies of /spl plusmn/2.5 V.
{"title":"Versatile second order filter structures for low-voltage multiple-input amplifiers","authors":"A. Al-Saqer, Nabil I. Khachab, J. G. Varghese","doi":"10.1109/ICECS.1996.582687","DOIUrl":"https://doi.org/10.1109/ICECS.1996.582687","url":null,"abstract":"Two second order filter architectures are presented with applications to double and single ended multiple input amplifier configurations. These circuits can be configured to perform BP, HP, LP and notch filter functions. The Gm tunability of the fully-complementary, Composite Folded Cascode (CFC) based amplifier test structures is achieved by a MOSR scheme with center-frequency variations in the upper Megahertz range, using power supplies of /spl plusmn/2.5 V.","PeriodicalId":402369,"journal":{"name":"Proceedings of Third International Conference on Electronics, Circuits, and Systems","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121246965","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-10-13DOI: 10.1109/ICECS.1996.582940
F. Koumboulis, M. G. Skarpetis
The problem of exact model matching for single input single output linear systems with nonlinear uncertain structure, via an independent of the uncertainties P-D state and output feedback, is studied. The necessary and sufficient conditions for the problem to have a solution, are established. The general expressions of the feedback matrices solving the problem are derived. For the special case of static state feedback, the respective results are also derived. For a permanent magnet DC motor with uncertain load inertia and viscosity, an independent of the uncertainties P-D feedback law is applied to yield a closed loop system transfer function which is equal to that of a desired model's.
{"title":"Robust exact model matching via P-D feedback with application to DC servo motor","authors":"F. Koumboulis, M. G. Skarpetis","doi":"10.1109/ICECS.1996.582940","DOIUrl":"https://doi.org/10.1109/ICECS.1996.582940","url":null,"abstract":"The problem of exact model matching for single input single output linear systems with nonlinear uncertain structure, via an independent of the uncertainties P-D state and output feedback, is studied. The necessary and sufficient conditions for the problem to have a solution, are established. The general expressions of the feedback matrices solving the problem are derived. For the special case of static state feedback, the respective results are also derived. For a permanent magnet DC motor with uncertain load inertia and viscosity, an independent of the uncertainties P-D feedback law is applied to yield a closed loop system transfer function which is equal to that of a desired model's.","PeriodicalId":402369,"journal":{"name":"Proceedings of Third International Conference on Electronics, Circuits, and Systems","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127130793","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-10-13DOI: 10.1109/ICECS.1996.584459
G. Rozinaj, A. Marcek
An original algorithm for the approximation of the discrete cosine transform (DCT) without multiplication is presented. The method is based on a recursive generator of discrete harmonic signals. The "speed/accuracy" ratio can be tuned due to input specifications. The actual accuracy and error analysis depend on the length of the DCT. We analyse the possibility of using our algorithm in JPEG image compression. However, application of the approximation method is possible in all problems using DCT. Our new approach to the DCT approximation is applicable to other transforms such as the DFT.
{"title":"Approximation of DCT without multiplication in JPEG","authors":"G. Rozinaj, A. Marcek","doi":"10.1109/ICECS.1996.584459","DOIUrl":"https://doi.org/10.1109/ICECS.1996.584459","url":null,"abstract":"An original algorithm for the approximation of the discrete cosine transform (DCT) without multiplication is presented. The method is based on a recursive generator of discrete harmonic signals. The \"speed/accuracy\" ratio can be tuned due to input specifications. The actual accuracy and error analysis depend on the length of the DCT. We analyse the possibility of using our algorithm in JPEG image compression. However, application of the approximation method is possible in all problems using DCT. Our new approach to the DCT approximation is applicable to other transforms such as the DFT.","PeriodicalId":402369,"journal":{"name":"Proceedings of Third International Conference on Electronics, Circuits, and Systems","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127140916","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-10-13DOI: 10.1109/ICECS.1996.582910
F. Koumboulis
In this paper the problem of disturbance rejection and data sensitivity is studied for the case of linear time invariant systems. Using a proportional state feedback law, the necessary and sufficient conditions for the problem to have a solution are established. The set of all allowable perturbations is explicitly characterized. An independent version of the perturbation special feedback law solving the problem for all allowable perturbations is derived. The necessary and sufficient conditions for disturbance rejection, data sensitivity and BIBO stability are established. A feedback law solving the later problem for all allowable perturbations is also derived.
{"title":"Characterization of the allowable perturbations for disturbance rejection and data sensitivity","authors":"F. Koumboulis","doi":"10.1109/ICECS.1996.582910","DOIUrl":"https://doi.org/10.1109/ICECS.1996.582910","url":null,"abstract":"In this paper the problem of disturbance rejection and data sensitivity is studied for the case of linear time invariant systems. Using a proportional state feedback law, the necessary and sufficient conditions for the problem to have a solution are established. The set of all allowable perturbations is explicitly characterized. An independent version of the perturbation special feedback law solving the problem for all allowable perturbations is derived. The necessary and sufficient conditions for disturbance rejection, data sensitivity and BIBO stability are established. A feedback law solving the later problem for all allowable perturbations is also derived.","PeriodicalId":402369,"journal":{"name":"Proceedings of Third International Conference on Electronics, Circuits, and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127366262","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-10-13DOI: 10.1109/ICECS.1996.582856
A. Demosthenous, R. Akbari-Dilmaghani, S. Smedley, John T. Taylor
A CMOS modular high-speed current-mode 2-input Winner-Take-All (2-WTA) circuit for use in VLSI tree-structure WTA networks is described. The classification speed of the design is not input pattern dependent, but is a function of the value of the largest current input only. The complexity of the proposed WTA is O(M), but unlike other architectures, mismatch errors accumulate at a rate proportional to log/sub 2/M. Since for large M this is a slowly increasing function of M, the proposed arrangement is well suited to large WTA systems. Simulations show that the proposed circuit can resolve input currents differing by less than 1/spl mu/A with only a small loss of operating speed. Detailed simulations and measured results of a single 2-WTA cell and of a complete 8-input tree WTA are presented.
{"title":"Enhanced modular CMOS current-mode winner-take-all network","authors":"A. Demosthenous, R. Akbari-Dilmaghani, S. Smedley, John T. Taylor","doi":"10.1109/ICECS.1996.582856","DOIUrl":"https://doi.org/10.1109/ICECS.1996.582856","url":null,"abstract":"A CMOS modular high-speed current-mode 2-input Winner-Take-All (2-WTA) circuit for use in VLSI tree-structure WTA networks is described. The classification speed of the design is not input pattern dependent, but is a function of the value of the largest current input only. The complexity of the proposed WTA is O(M), but unlike other architectures, mismatch errors accumulate at a rate proportional to log/sub 2/M. Since for large M this is a slowly increasing function of M, the proposed arrangement is well suited to large WTA systems. Simulations show that the proposed circuit can resolve input currents differing by less than 1/spl mu/A with only a small loss of operating speed. Detailed simulations and measured results of a single 2-WTA cell and of a complete 8-input tree WTA are presented.","PeriodicalId":402369,"journal":{"name":"Proceedings of Third International Conference on Electronics, Circuits, and Systems","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124972853","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-10-13DOI: 10.1109/ICECS.1996.582749
C. Vertan, M. Malciu, T. Zaharia, V. Buzuloiu
The processing and analysis of vector valued signals has become in the last decade a major field of interest. The direct extension of classical processing methods for the scalar signals is not always possible. The mathematical morphology viewed as a processing technique for gray images is such that it cannot be extended easily. In this paper we present an approach to the vector mathematical morphology based on clustering techniques in the signal sample space.
{"title":"A clustering approach to vector mathematical morphology","authors":"C. Vertan, M. Malciu, T. Zaharia, V. Buzuloiu","doi":"10.1109/ICECS.1996.582749","DOIUrl":"https://doi.org/10.1109/ICECS.1996.582749","url":null,"abstract":"The processing and analysis of vector valued signals has become in the last decade a major field of interest. The direct extension of classical processing methods for the scalar signals is not always possible. The mathematical morphology viewed as a processing technique for gray images is such that it cannot be extended easily. In this paper we present an approach to the vector mathematical morphology based on clustering techniques in the signal sample space.","PeriodicalId":402369,"journal":{"name":"Proceedings of Third International Conference on Electronics, Circuits, and Systems","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125092102","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-10-13DOI: 10.1109/ICECS.1996.584563
Minyoung Song, Geun-Soon Kang, Seongwon Kim, Euro Joe, Bong-Soon Kang
Energy Economized Pass-transistor Logic (EEPL) is proposed. Adopting the principle of regenerative positive feedback with pMOS switches, we reduce the power in comparison with CPL and SRPL. To demonstrate the performance of EEPL, a low power 7-bit serial counter is designed. The operating speed is about 250 MHz with 0.6 /spl mu/m 3.3 V CMOS process.
提出了一种节能通管逻辑(EEPL)。采用pMOS开关的再生正反馈原理，与CPL和SRPL相比，我们降低了功率。为了验证EEPL的性能，设计了一个低功耗的7位串行计数器。工作速度约为250 MHz，采用0.6 /spl mu/m 3.3 V CMOS工艺。
{"title":"Design of a low power 7-bit serial counter with energy economized pass-transistor logic (EEPL)","authors":"Minyoung Song, Geun-Soon Kang, Seongwon Kim, Euro Joe, Bong-Soon Kang","doi":"10.1109/ICECS.1996.584563","DOIUrl":"https://doi.org/10.1109/ICECS.1996.584563","url":null,"abstract":"Energy Economized Pass-transistor Logic (EEPL) is proposed. Adopting the principle of regenerative positive feedback with pMOS switches, we reduce the power in comparison with CPL and SRPL. To demonstrate the performance of EEPL, a low power 7-bit serial counter is designed. The operating speed is about 250 MHz with 0.6 /spl mu/m 3.3 V CMOS process.","PeriodicalId":402369,"journal":{"name":"Proceedings of Third International Conference on Electronics, Circuits, and Systems","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122495251","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-10-13DOI: 10.1109/ICECS.1996.584560
S. Kiartzis, C. Zoumas, A. Bakirtzis, V. Petridis
This paper presents the development of an Artificial Neural Network (ANN) based short-term load forecasting model for the Dispatching Center of the Greek Public Power Corporation (PPC) in the island of Crete. The model can forecast daily load profiles with a lead time of one to seven days. Experiences gained during the development of the model regarding the selection of the input variables, the ANN structure, and the training data set pre-processing are described in the paper.
{"title":"Data pre-processing for short-term load forecasting in an autonomous power system using artificial neural networks","authors":"S. Kiartzis, C. Zoumas, A. Bakirtzis, V. Petridis","doi":"10.1109/ICECS.1996.584560","DOIUrl":"https://doi.org/10.1109/ICECS.1996.584560","url":null,"abstract":"This paper presents the development of an Artificial Neural Network (ANN) based short-term load forecasting model for the Dispatching Center of the Greek Public Power Corporation (PPC) in the island of Crete. The model can forecast daily load profiles with a lead time of one to seven days. Experiences gained during the development of the model regarding the selection of the input variables, the ANN structure, and the training data set pre-processing are described in the paper.","PeriodicalId":402369,"journal":{"name":"Proceedings of Third International Conference on Electronics, Circuits, and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122835542","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-10-13DOI: 10.1109/ICECS.1996.582815
A. Maniatopoulos, T. Antonakopoulos, V. Makios
In this paper the performance analysis of a new high-speed cell-based interface is presented. The so called VIRUS interface can be used for replacing existing physical layer interfaces of cell-based networks, since its functions result in lower hardware complexity and, thus, it can be easily used at higher data rates. The interface analysis is mainly focused on the evaluation of the proposed synchronization method as well as on the effects of the line coding scheme on the synchronization procedure. The results prove the advantage of the proposed interface when used for cell-based communication networks and high-speed point-to-point interfaces.
{"title":"Performance analysis of the synchronization mechanism used at the VIRUS interface","authors":"A. Maniatopoulos, T. Antonakopoulos, V. Makios","doi":"10.1109/ICECS.1996.582815","DOIUrl":"https://doi.org/10.1109/ICECS.1996.582815","url":null,"abstract":"In this paper the performance analysis of a new high-speed cell-based interface is presented. The so called VIRUS interface can be used for replacing existing physical layer interfaces of cell-based networks, since its functions result in lower hardware complexity and, thus, it can be easily used at higher data rates. The interface analysis is mainly focused on the evaluation of the proposed synchronization method as well as on the effects of the line coding scheme on the synchronization procedure. The results prove the advantage of the proposed interface when used for cell-based communication networks and high-speed point-to-point interfaces.","PeriodicalId":402369,"journal":{"name":"Proceedings of Third International Conference on Electronics, Circuits, and Systems","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114185164","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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