3D via etch development for 3D circuit integration in FDSOI

J. Knecht, D. Yost, J. Burns, C.K. Chen, C. Keast, K. Warner
{"title":"3D via etch development for 3D circuit integration in FDSOI","authors":"J. Knecht, D. Yost, J. Burns, C.K. Chen, C. Keast, K. Warner","doi":"10.1109/SOI.2005.1563552","DOIUrl":null,"url":null,"abstract":"This paper describes the development of the 3D via etch process.The oxide via etch was developed in a Trikon Technologies low pressure, high density, helicon-based cluster tool. A response surface design-of-experiments (DOE) was performed varying etch pressure and wafer bias to examine their effect on etch profile and etch rates. An anisotropic etch is essential for high packing density. There was an excellent fit between the data and the model. Low pressure and high bias were required to give vertical profiles. Higher etch pressure caused excessive polymer deposition resulting in etch stop. Low wafer bias could not remove the deposited polymer fast enough, also resulting in etch stop.","PeriodicalId":116606,"journal":{"name":"2005 IEEE International SOI Conference Proceedings","volume":"22 10","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2005 IEEE International SOI Conference Proceedings","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SOI.2005.1563552","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 7

Abstract

This paper describes the development of the 3D via etch process.The oxide via etch was developed in a Trikon Technologies low pressure, high density, helicon-based cluster tool. A response surface design-of-experiments (DOE) was performed varying etch pressure and wafer bias to examine their effect on etch profile and etch rates. An anisotropic etch is essential for high packing density. There was an excellent fit between the data and the model. Low pressure and high bias were required to give vertical profiles. Higher etch pressure caused excessive polymer deposition resulting in etch stop. Low wafer bias could not remove the deposited polymer fast enough, also resulting in etch stop.
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
FDSOI中3D电路集成的蚀刻开发
本文介绍了三维刻蚀工艺的发展。通过蚀刻的氧化物是在Trikon Technologies低压、高密度、螺旋基簇状工具中开发的。在不同的蚀刻压力和晶圆偏置下进行了响应面实验设计(DOE),考察了它们对蚀刻轮廓和蚀刻速率的影响。各向异性蚀刻对于高包装密度是必不可少的。数据和模型之间非常吻合。需要低压和高偏置来获得垂直剖面。较高的蚀刻压力造成过多的聚合物沉积,导致蚀刻停止。低晶圆偏压不能足够快地去除沉积的聚合物,也会导致蚀刻停止。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 去求助
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
The effect of integration of strontium-bismuth-tantalate capacitors onto SOI wafers A novel self-aligned substrate-diode structure for SOI technologies Development of stacking faults in strained silicon layers 3D via etch development for 3D circuit integration in FDSOI Stress technology impact on device performance and reliability for <100> sub-90nm SOI CMOSFETs
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1