Pub Date : 2006-07-24DOI: 10.1109/AERO.2006.1655955
V. Joshi, M. Ohno, J. Ida, Y. Nagatomo, K. Strauss
We report for the first time the successful integration of strontium-bismuth-tantalate ferroelectric capacitors on an SOI substrate. We have verified that the unique processing requirements of SBT capacitors do not affect the properties of the surrounding FD-SOI transistors, and, conversely, we have verified that the SOI processing does not affect the quality of the SBT capacitors.
{"title":"The effect of integration of strontium-bismuth-tantalate capacitors onto SOI wafers","authors":"V. Joshi, M. Ohno, J. Ida, Y. Nagatomo, K. Strauss","doi":"10.1109/AERO.2006.1655955","DOIUrl":"https://doi.org/10.1109/AERO.2006.1655955","url":null,"abstract":"We report for the first time the successful integration of strontium-bismuth-tantalate ferroelectric capacitors on an SOI substrate. We have verified that the unique processing requirements of SBT capacitors do not affect the properties of the surrounding FD-SOI transistors, and, conversely, we have verified that the SOI processing does not affect the quality of the SBT capacitors.","PeriodicalId":116606,"journal":{"name":"2005 IEEE International SOI Conference Proceedings","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132816689","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-27DOI: 10.1109/SOI.2005.1563597
A. Dixit, K. Anil, N. Collaert, R. Rooyackers, F. Leys, I. Ferain, A. De Keersgieter, T. Hoffmann, R. Loo, M. Goodwin, P. Zimmerman, M. Caymax, K. De Meyer, M. Jurczak, S. Biesemans
We report on a set of process improvements leading to parasitic S/D resistance reduction in n-channel MuGFETs with 60 nm tall and 15 nm wide fins. We experimentally determine the contributions to the parasitic S/D resistance arising from the specific regions of the S/D geometry. A 50% reduction in the S/D resistance (from 1235 to 600 /spl Omega/-/spl mu/m) is achieved by introducing various scaled processes, including EOT reduction, elevated S/D, undoped fins and removal of halos, reduction in S/D spacer width, and smaller gate lengths. The combination of these process enhancements leads to a 2/spl times/ increase in I/sub DSAT/, measured at constant I/sub OFF/ (=1nA//spl mu/m) and V/sub DD/=1.3V.
{"title":"Parasitic source/drain resistance reduction in n-channel SOI MuGFETs with 15nm wide fins","authors":"A. Dixit, K. Anil, N. Collaert, R. Rooyackers, F. Leys, I. Ferain, A. De Keersgieter, T. Hoffmann, R. Loo, M. Goodwin, P. Zimmerman, M. Caymax, K. De Meyer, M. Jurczak, S. Biesemans","doi":"10.1109/SOI.2005.1563597","DOIUrl":"https://doi.org/10.1109/SOI.2005.1563597","url":null,"abstract":"We report on a set of process improvements leading to parasitic S/D resistance reduction in n-channel MuGFETs with 60 nm tall and 15 nm wide fins. We experimentally determine the contributions to the parasitic S/D resistance arising from the specific regions of the S/D geometry. A 50% reduction in the S/D resistance (from 1235 to 600 /spl Omega/-/spl mu/m) is achieved by introducing various scaled processes, including EOT reduction, elevated S/D, undoped fins and removal of halos, reduction in S/D spacer width, and smaller gate lengths. The combination of these process enhancements leads to a 2/spl times/ increase in I/sub DSAT/, measured at constant I/sub OFF/ (=1nA//spl mu/m) and V/sub DD/=1.3V.","PeriodicalId":116606,"journal":{"name":"2005 IEEE International SOI Conference Proceedings","volume":"4 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121008261","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-27DOI: 10.1109/SOI.2005.1563571
T. Schulz, W. Xiong, C. Cleavelin, K. Schruefer, M. Gostkowski, K. Matthews, G. Gebara, R. J. Zaman, P. Patruno, A. Chaudhry, A. Woo, J. Colinge
Fin thickness non-uniformity is a potential shortcoming of vertical multiple-gate devices such as FinFETs and tri-gate FETs. In this paper a test structure with intentionally misaligned gates is used to investigate the sensitivity of electrical characteristics on fin thickness variations.
{"title":"Fin thickness asymmetry effects in multiple-gate SOI FETs (MuGFETs)","authors":"T. Schulz, W. Xiong, C. Cleavelin, K. Schruefer, M. Gostkowski, K. Matthews, G. Gebara, R. J. Zaman, P. Patruno, A. Chaudhry, A. Woo, J. Colinge","doi":"10.1109/SOI.2005.1563571","DOIUrl":"https://doi.org/10.1109/SOI.2005.1563571","url":null,"abstract":"Fin thickness non-uniformity is a potential shortcoming of vertical multiple-gate devices such as FinFETs and tri-gate FETs. In this paper a test structure with intentionally misaligned gates is used to investigate the sensitivity of electrical characteristics on fin thickness variations.","PeriodicalId":116606,"journal":{"name":"2005 IEEE International SOI Conference Proceedings","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127166248","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-27DOI: 10.1109/SOI.2005.1563528
C. Chen, R. Chang, P. Wyatt, C.K. Chen, D. Yost, J.M. Knech, C. Keast
The impact of body contacts on the floating body effect of fully depleted (FD) SOI at high frequencies is studied. It is found that the floating body effect is negligibly small for FDSOI FETs and the body contact (BC) increased parasitic capacitance and degraded the performance. We show that the linearity of an X-band amplifier, fabricated with a 180-nm FDSOI technology, is unchanged by the BC in continuous wave and pulse mode operations.
{"title":"Floating body effects on the RF performance of FDSOI RF amplifiers","authors":"C. Chen, R. Chang, P. Wyatt, C.K. Chen, D. Yost, J.M. Knech, C. Keast","doi":"10.1109/SOI.2005.1563528","DOIUrl":"https://doi.org/10.1109/SOI.2005.1563528","url":null,"abstract":"The impact of body contacts on the floating body effect of fully depleted (FD) SOI at high frequencies is studied. It is found that the floating body effect is negligibly small for FDSOI FETs and the body contact (BC) increased parasitic capacitance and degraded the performance. We show that the linearity of an X-band amplifier, fabricated with a 180-nm FDSOI technology, is unchanged by the BC in continuous wave and pulse mode operations.","PeriodicalId":116606,"journal":{"name":"2005 IEEE International SOI Conference Proceedings","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127495305","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-27DOI: 10.1109/SOI.2005.1563521
I. Åberg, Z. Cheng, T. Langdo, I. Lauer, Anthony Lochtefeld, D. Antoniadis, J. Hoyt
In this work, we study both FD- and PD-SSOI with aggressive T/sub Si/ of up to 135 nm for 14% SSOI (14% Ge equivalent strain). We have demonstrated that mobility in 14% SSOI is independent of the strained Si thickness, even for as grown films 10/spl times/ thicker than the critical thickness. Off-state current also remains independent of T/sub Si/. The successful fabrication of PD-SSOI with electron mobility enhancement maintained at 1.5/spl times/, for high channel doping and strained Si thickness up to 135 nm, was also demonstrated, showing promise for thicker film PD-SOI applications.
{"title":"Transport and leakage in super-critical thickness strained silicon directly on insulator MOSFETs with strained Si thickness up to 135 nm","authors":"I. Åberg, Z. Cheng, T. Langdo, I. Lauer, Anthony Lochtefeld, D. Antoniadis, J. Hoyt","doi":"10.1109/SOI.2005.1563521","DOIUrl":"https://doi.org/10.1109/SOI.2005.1563521","url":null,"abstract":"In this work, we study both FD- and PD-SSOI with aggressive T/sub Si/ of up to 135 nm for 14% SSOI (14% Ge equivalent strain). We have demonstrated that mobility in 14% SSOI is independent of the strained Si thickness, even for as grown films 10/spl times/ thicker than the critical thickness. Off-state current also remains independent of T/sub Si/. The successful fabrication of PD-SSOI with electron mobility enhancement maintained at 1.5/spl times/, for high channel doping and strained Si thickness up to 135 nm, was also demonstrated, showing promise for thicker film PD-SOI applications.","PeriodicalId":116606,"journal":{"name":"2005 IEEE International SOI Conference Proceedings","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125316796","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-27DOI: 10.1109/SOI.2005.1563578
Sung Hwan Kim, C. Oh, K. Yeo, D. Choi, Min Sang Kim, Sung Min Kim, J. Choe, J. Han, Young-pil Kim, Dong-Won Kim, Donggun Park, B. Ryu
We proposed and successfully demonstrated partially insulated and bulk MOSFETs with multiple V/sub th/s, I/sub on/s, and I/sub Off/s by using partial SOI process without complex process and SOI wafer. Both nMOS and pMOS applicable to the HP and LSTP transistors were simultaneously implemented on the same wafer with the same process except partial SOI process. These results must be very useful to implement IC systems requiring various specifications of V/sub TH/s, I/sub On/s, and I/sub Off/s.
{"title":"Lateral integration of partially insulated and bulk MOSFETs using partial SOI process","authors":"Sung Hwan Kim, C. Oh, K. Yeo, D. Choi, Min Sang Kim, Sung Min Kim, J. Choe, J. Han, Young-pil Kim, Dong-Won Kim, Donggun Park, B. Ryu","doi":"10.1109/SOI.2005.1563578","DOIUrl":"https://doi.org/10.1109/SOI.2005.1563578","url":null,"abstract":"We proposed and successfully demonstrated partially insulated and bulk MOSFETs with multiple V/sub th/s, I/sub on/s, and I/sub Off/s by using partial SOI process without complex process and SOI wafer. Both nMOS and pMOS applicable to the HP and LSTP transistors were simultaneously implemented on the same wafer with the same process except partial SOI process. These results must be very useful to implement IC systems requiring various specifications of V/sub TH/s, I/sub On/s, and I/sub Off/s.","PeriodicalId":116606,"journal":{"name":"2005 IEEE International SOI Conference Proceedings","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125401138","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-27DOI: 10.1109/SOI.2005.1563529
A. Engelstein, J. Fournier, V. Knopik, C. Raynaud
The goal of this paper is to focus on the advantages of SOI technologies for high speed digital circuits for RF application, through the study of the consumption of 10 GHz frequency dividers. Dynamic and static structures are implemented in bulk and SOI CMOS 0.13 /spl mu/m technologies, and the measured consumptions are compared. As the capacitance of the drain-source diffusions and interconnections are reduced in SOI because of the BOX, dynamic consumption reductions of 20 % and 25 % are measured between bulk and SOI technologies, respectively for the dynamic and static structure.
{"title":"A comparison of 10 GHz frequency dividers in bulk and SOI 0.13 /spl mu/m CMOS technologies","authors":"A. Engelstein, J. Fournier, V. Knopik, C. Raynaud","doi":"10.1109/SOI.2005.1563529","DOIUrl":"https://doi.org/10.1109/SOI.2005.1563529","url":null,"abstract":"The goal of this paper is to focus on the advantages of SOI technologies for high speed digital circuits for RF application, through the study of the consumption of 10 GHz frequency dividers. Dynamic and static structures are implemented in bulk and SOI CMOS 0.13 /spl mu/m technologies, and the measured consumptions are compared. As the capacitance of the drain-source diffusions and interconnections are reduced in SOI because of the BOX, dynamic consumption reductions of 20 % and 25 % are measured between bulk and SOI technologies, respectively for the dynamic and static structure.","PeriodicalId":116606,"journal":{"name":"2005 IEEE International SOI Conference Proceedings","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125535466","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-27DOI: 10.1109/SOI.2005.1563586
V. Raghunathan, R. Claps, O. Boyraz, P. Koonath, D. Dimitropoulos, B. Jalali
Stimulated Raman scattering in SOI waveguides has received significant attention recently with the demonstration of pulsed, continuous wave Raman lasers and high gain Raman amplification. However, the limited bandwidth of the Raman signal in silicon (/spl sim/105GHz) renders this scheme unsuitable for broadband WDM amplification unless multi-pumping scheme is employed. Large pulsed gain and lasing have been reported in GeSi waveguides. The SiGe on SOI platform represents a Raman medium with a flexible gain spectrum.
{"title":"Raman amplification and lasing in SiGe-on-insulator waveguides","authors":"V. Raghunathan, R. Claps, O. Boyraz, P. Koonath, D. Dimitropoulos, B. Jalali","doi":"10.1109/SOI.2005.1563586","DOIUrl":"https://doi.org/10.1109/SOI.2005.1563586","url":null,"abstract":"Stimulated Raman scattering in SOI waveguides has received significant attention recently with the demonstration of pulsed, continuous wave Raman lasers and high gain Raman amplification. However, the limited bandwidth of the Raman signal in silicon (/spl sim/105GHz) renders this scheme unsuitable for broadband WDM amplification unless multi-pumping scheme is employed. Large pulsed gain and lasing have been reported in GeSi waveguides. The SiGe on SOI platform represents a Raman medium with a flexible gain spectrum.","PeriodicalId":116606,"journal":{"name":"2005 IEEE International SOI Conference Proceedings","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128581158","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-27DOI: 10.1109/SOI.2005.1563539
J. B. Kuang, K. Kim, C. Chuang, H. Ngo, K. Nowka
In this paper, conditional keeper, charge sharing prevention, and clock load reduction techniques for symmetrical and asymmetrical DG devices have been presented. Performance benefit, noise immunity, area and power efficiency can be achieved when technology features are judiciously utilized in the design of dynamic circuits.
{"title":"Dynamic circuit techniques using independently controlled double-gate devices","authors":"J. B. Kuang, K. Kim, C. Chuang, H. Ngo, K. Nowka","doi":"10.1109/SOI.2005.1563539","DOIUrl":"https://doi.org/10.1109/SOI.2005.1563539","url":null,"abstract":"In this paper, conditional keeper, charge sharing prevention, and clock load reduction techniques for symmetrical and asymmetrical DG devices have been presented. Performance benefit, noise immunity, area and power efficiency can be achieved when technology features are judiciously utilized in the design of dynamic circuits.","PeriodicalId":116606,"journal":{"name":"2005 IEEE International SOI Conference Proceedings","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129887996","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-27DOI: 10.1109/SOI.2005.1563518
C. Gunn
Luxtera has used Freescale Semiconductor's production 0.13/spl mu/m SOI process to implement optical communications capability for high bandwidth LAN, SAN, shelf-to-shelf and chip-to-chip communications. These optical transceiver cores operate at 10Gbps and offer superior reach, power consumption, latency, die area, and scalability compared to emerging standards for electrical interconnect. They are monolithically fabricated alongside SOI CMOS circuitry in the same die. Thus, for the first time in history, high speed optical communications directly between silicon die can be accomplished at a price/performance point superior to traditional electrical interconnect.
{"title":"CMOS photonics/spl trade/ - SOI learns a new trick","authors":"C. Gunn","doi":"10.1109/SOI.2005.1563518","DOIUrl":"https://doi.org/10.1109/SOI.2005.1563518","url":null,"abstract":"Luxtera has used Freescale Semiconductor's production 0.13/spl mu/m SOI process to implement optical communications capability for high bandwidth LAN, SAN, shelf-to-shelf and chip-to-chip communications. These optical transceiver cores operate at 10Gbps and offer superior reach, power consumption, latency, die area, and scalability compared to emerging standards for electrical interconnect. They are monolithically fabricated alongside SOI CMOS circuitry in the same die. Thus, for the first time in history, high speed optical communications directly between silicon die can be accomplished at a price/performance point superior to traditional electrical interconnect.","PeriodicalId":116606,"journal":{"name":"2005 IEEE International SOI Conference Proceedings","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116207370","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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