A gm/ID Design Methodology for 28 nm FD-SOI CMOS Resistive Feedback LNAs

Abstract

This paper presents a simple and efficient methodology for Resistive Feedback LNAs (RF-LNAs) design which uses the inversion level of the transistor as a design parameter in order to optimize the energy efficiency. The method uses a simple 4 parameter-based model valid in all regions of operation and allows a preliminary sizing based on an analytical study. A practical design in a 28 nm FD-SOI technology shows that this methodology is well suited for design at low to moderate inversion level in an advanced technology for which simulation-based studies are often used by designer as early sizing stage. The designed LNA consumes 0.57 mW and achieves an 18.4 dB gain with 3.3 dB of NF.