Pub Date : 2021-11-28DOI: 10.1109/icecs53924.2021.9665523
N. Prette, D. Valsesia, T. Bianchi
This work proposes a novel Deep Learning technique to increase the efficiency of currently available video compression techniques based on motion compensation. The goal is to improve the frame prediction task, whereby a more accurate prediction of the motion from the reference frames to the target frame allows to reduce the rate needed to encode the residual. This is achieved by means of a convolutional neural network (CNN) architecture that processes the basic block-based motion-compensated prediction of the current frame as well as predictions from past reference frames. This method allows to reduce typical artifacts such as blockiness, and achieves a more accurate prediction of motion thanks to the representation capabilities of CNNs, leading to smaller prediction residuals. Preliminary results show that the proposed approach is capable of providing BD-rate gains up to 6%.
{"title":"Deep Multiframe Enhancement for Motion Prediction in Video Compression","authors":"N. Prette, D. Valsesia, T. Bianchi","doi":"10.1109/icecs53924.2021.9665523","DOIUrl":"https://doi.org/10.1109/icecs53924.2021.9665523","url":null,"abstract":"This work proposes a novel Deep Learning technique to increase the efficiency of currently available video compression techniques based on motion compensation. The goal is to improve the frame prediction task, whereby a more accurate prediction of the motion from the reference frames to the target frame allows to reduce the rate needed to encode the residual. This is achieved by means of a convolutional neural network (CNN) architecture that processes the basic block-based motion-compensated prediction of the current frame as well as predictions from past reference frames. This method allows to reduce typical artifacts such as blockiness, and achieves a more accurate prediction of motion thanks to the representation capabilities of CNNs, leading to smaller prediction residuals. Preliminary results show that the proposed approach is capable of providing BD-rate gains up to 6%.","PeriodicalId":448558,"journal":{"name":"2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-11-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127258575","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-11-28DOI: 10.1109/icecs53924.2021.9665606
Ahmed Nasser, Karim Ahmed Fadel, Karim Abbas, K. Ahmed, Mohamed Abdelsalam, Mahmoud Gaber
Machine learning (ML) algorithms have proven to be a concrete component in various fields that aim to be fully automated. Therefore, many researchers have shed the light on the modifications of ML algorithms to be fully automated for more complicated tasks. However, the acceleration of such algorithms is extremely hard due to the high computations and memory required. This paper implements automated flow using Perl scripts and generated LeNet-5 (A Convolutional Neural Network Model). Our target is high throughput, configurable and scalable RTL design that is generated by Perl scripts. Our flow is designing and verifying using Veloce emulator.
{"title":"An Automated Flow for Configuration and Generation of CNN based AI accelerators for HW Emulation & FPGA Prototyping","authors":"Ahmed Nasser, Karim Ahmed Fadel, Karim Abbas, K. Ahmed, Mohamed Abdelsalam, Mahmoud Gaber","doi":"10.1109/icecs53924.2021.9665606","DOIUrl":"https://doi.org/10.1109/icecs53924.2021.9665606","url":null,"abstract":"Machine learning (ML) algorithms have proven to be a concrete component in various fields that aim to be fully automated. Therefore, many researchers have shed the light on the modifications of ML algorithms to be fully automated for more complicated tasks. However, the acceleration of such algorithms is extremely hard due to the high computations and memory required. This paper implements automated flow using Perl scripts and generated LeNet-5 (A Convolutional Neural Network Model). Our target is high throughput, configurable and scalable RTL design that is generated by Perl scripts. Our flow is designing and verifying using Veloce emulator.","PeriodicalId":448558,"journal":{"name":"2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-11-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127349474","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-11-28DOI: 10.1109/icecs53924.2021.9665468
V. Thanasoulis, B. Vogginger, J. Partzsch, C. Mayr
Neuromorphic engineering implements large-scale systems that provide a high integration density of power efficient synapse-and-neuron blocks. This represents a promising alternative to the numerical simulations for studying the dynamics of spiking neural networks. A key aspect of these systems is the implementation of communication and routing of pulse events produced by the neural network. In this paper we present a measurement methodology and results of a neural benchmark that tests the configurable delays, multicasting and connectivity implemented by a routing logic for neuromorphic hardware. Pulses are handled according to their timestamp and transmitted with configurable delays and routing to different post-synaptic neurons. The results show the suitability of communication and routing logic for delay-based neural computation and point out effects of time discretization in resolution of pulse timestamps.
{"title":"Delay-Based Neural Computation: Pulse Routing Architecture and Benchmark Application in FPGA","authors":"V. Thanasoulis, B. Vogginger, J. Partzsch, C. Mayr","doi":"10.1109/icecs53924.2021.9665468","DOIUrl":"https://doi.org/10.1109/icecs53924.2021.9665468","url":null,"abstract":"Neuromorphic engineering implements large-scale systems that provide a high integration density of power efficient synapse-and-neuron blocks. This represents a promising alternative to the numerical simulations for studying the dynamics of spiking neural networks. A key aspect of these systems is the implementation of communication and routing of pulse events produced by the neural network. In this paper we present a measurement methodology and results of a neural benchmark that tests the configurable delays, multicasting and connectivity implemented by a routing logic for neuromorphic hardware. Pulses are handled according to their timestamp and transmitted with configurable delays and routing to different post-synaptic neurons. The results show the suitability of communication and routing logic for delay-based neural computation and point out effects of time discretization in resolution of pulse timestamps.","PeriodicalId":448558,"journal":{"name":"2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-11-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124901652","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-11-28DOI: 10.1109/icecs53924.2021.9665627
Tianfang Peng, Zheng You
MEMS stoppers are commonly used structures to prevent failures caused by mechanical overload such as shock and pressure. However, the numerical research of the stoppers could be computationally costly and non-convergent, since it involves non-linear mechanical features such as contact and collision. This poses difficulties to the reliability design and optimization of MEMS. This paper proposes a parametric model of MEMS stoppers that is computationally efficient for reliability design. The model converts the material and geometric characteristics of the stopper into a nonlinear spring system. The efficiency and convergence of numerical computation of the MEMS structure with stoppers were effectively improved through both static and transient FEM research examples. The stress distribution and transient displacement response obtained by this model were in good agreement with the calculation results of traditional contact algorithm in FEM examples. The overload-resistance of MEMS stoppers were further analyzed. Finally, we optimized the design of MEMS stopper's shape and stiffness based on the parametric model. The model proposed in this study is suitable for the design and optimization of the anti-overload structure of MEMS.
{"title":"A Computationally Efficient Model of MEMS Stopper for Reliability Optimization","authors":"Tianfang Peng, Zheng You","doi":"10.1109/icecs53924.2021.9665627","DOIUrl":"https://doi.org/10.1109/icecs53924.2021.9665627","url":null,"abstract":"MEMS stoppers are commonly used structures to prevent failures caused by mechanical overload such as shock and pressure. However, the numerical research of the stoppers could be computationally costly and non-convergent, since it involves non-linear mechanical features such as contact and collision. This poses difficulties to the reliability design and optimization of MEMS. This paper proposes a parametric model of MEMS stoppers that is computationally efficient for reliability design. The model converts the material and geometric characteristics of the stopper into a nonlinear spring system. The efficiency and convergence of numerical computation of the MEMS structure with stoppers were effectively improved through both static and transient FEM research examples. The stress distribution and transient displacement response obtained by this model were in good agreement with the calculation results of traditional contact algorithm in FEM examples. The overload-resistance of MEMS stoppers were further analyzed. Finally, we optimized the design of MEMS stopper's shape and stiffness based on the parametric model. The model proposed in this study is suitable for the design and optimization of the anti-overload structure of MEMS.","PeriodicalId":448558,"journal":{"name":"2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-11-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126708476","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-11-28DOI: 10.1109/icecs53924.2021.9665571
Mustafa Oz, E. Bonizzoni, F. Maloberti, Alper Akdikmen, Jianping Li
A low offset voltage comparator with programmable hysteresis is analyzed, simulated, and presented. The comparator employs a new method for creating the hysteresis and its low-to-high and high-to-low transition threshold levels can be controlled independently even after fabrication. The circuit uses an NMOS and a PMOS preamplifier to accomplish the rail-to-rail operation. The comparator is designed and simulated in a conventional $0.13-mumathrm{m}$ CMOS process with a 3.3-V supply voltage. Monte Carlo simulations show that the comparator's random offset is $46.3 mumathrm{V}$ and its response time is 137 ns when the hysteresis is set to zero. The static current consumption is $11.2 mumathrm{A}$ from a 3.3-V power supply. All the hysteresis levels are obtained with good precision.
{"title":"A Rail-to-Rail CMOS Voltage Comparator with Programmable Hysteresis","authors":"Mustafa Oz, E. Bonizzoni, F. Maloberti, Alper Akdikmen, Jianping Li","doi":"10.1109/icecs53924.2021.9665571","DOIUrl":"https://doi.org/10.1109/icecs53924.2021.9665571","url":null,"abstract":"A low offset voltage comparator with programmable hysteresis is analyzed, simulated, and presented. The comparator employs a new method for creating the hysteresis and its low-to-high and high-to-low transition threshold levels can be controlled independently even after fabrication. The circuit uses an NMOS and a PMOS preamplifier to accomplish the rail-to-rail operation. The comparator is designed and simulated in a conventional $0.13-mumathrm{m}$ CMOS process with a 3.3-V supply voltage. Monte Carlo simulations show that the comparator's random offset is $46.3 mumathrm{V}$ and its response time is 137 ns when the hysteresis is set to zero. The static current consumption is $11.2 mumathrm{A}$ from a 3.3-V power supply. All the hysteresis levels are obtained with good precision.","PeriodicalId":448558,"journal":{"name":"2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-11-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122412251","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-11-28DOI: 10.1109/icecs53924.2021.9665517
Gazmend Alia, Andi Buzo, H. Maier-Flaig, Klaus-Willi Pieper, L. Maurer, G. Pelz
The need for more accurate simulations has pushed scientists and engineers to design better, more accurate and more complex MOSFET compact models. This has been supported by the big improvements in computational power and speed in the last decades. The number of parameters of the compact models has increased to hundreds and thousands and it is far beyond what the human mind can handle. As a results, the calibration of the models to represent the real characteristics of the device, also known as parameter extraction, is a complex and time consuming task. To solve this problem, many automatic techniques have been tried and the most promising ones are based on genetic algorithms. Genetic algorithms on the other side, although appropriate for such tasks, require a large number of simulations to converge to a good solution. In this paper we propose a methodology to drastically reduce the number of simulations by introducing a combination of genetic algorithms and surrogate models as classifiers. The state of the art about the combination of surrogate models and genetic algorithms is exclusively focused on how to use surrogate models to substitute the expensive simulations. Our novel approach consists on adding a classifier layer between the genetic algorithm and the simulations, which filters out a significant number of non-promising parameter sets that do not need to be simulated at all. In this research, differential evolution was used as the genetic algorithm and after a careful evaluation of several classifier types, the decision tree classifier was selected as the best performing one. The method was tested with two complex real life problems, BSIM4 and HiSIM-HV MOSFET compact models, and the results show that up to 70% of the simulations could be eliminated without disturbing the convergence of the algorithm and maintaining the accuracy of the solution.
{"title":"Machine learning-based acceleration of Genetic Algorithms for Parameter Extraction of highly dimensional MOSFET Compact Models","authors":"Gazmend Alia, Andi Buzo, H. Maier-Flaig, Klaus-Willi Pieper, L. Maurer, G. Pelz","doi":"10.1109/icecs53924.2021.9665517","DOIUrl":"https://doi.org/10.1109/icecs53924.2021.9665517","url":null,"abstract":"The need for more accurate simulations has pushed scientists and engineers to design better, more accurate and more complex MOSFET compact models. This has been supported by the big improvements in computational power and speed in the last decades. The number of parameters of the compact models has increased to hundreds and thousands and it is far beyond what the human mind can handle. As a results, the calibration of the models to represent the real characteristics of the device, also known as parameter extraction, is a complex and time consuming task. To solve this problem, many automatic techniques have been tried and the most promising ones are based on genetic algorithms. Genetic algorithms on the other side, although appropriate for such tasks, require a large number of simulations to converge to a good solution. In this paper we propose a methodology to drastically reduce the number of simulations by introducing a combination of genetic algorithms and surrogate models as classifiers. The state of the art about the combination of surrogate models and genetic algorithms is exclusively focused on how to use surrogate models to substitute the expensive simulations. Our novel approach consists on adding a classifier layer between the genetic algorithm and the simulations, which filters out a significant number of non-promising parameter sets that do not need to be simulated at all. In this research, differential evolution was used as the genetic algorithm and after a careful evaluation of several classifier types, the decision tree classifier was selected as the best performing one. The method was tested with two complex real life problems, BSIM4 and HiSIM-HV MOSFET compact models, and the results show that up to 70% of the simulations could be eliminated without disturbing the convergence of the algorithm and maintaining the accuracy of the solution.","PeriodicalId":448558,"journal":{"name":"2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-11-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122643395","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-11-28DOI: 10.1109/icecs53924.2021.9665521
Salwa K. Al Khatib, Tarek Naous, R. Shubair, H. M. E. Misilmani
Breast Microwave Imaging (BMI) has emerged as a viable alternative to conventional breast cancer screening techniques due to its favorable features and a higher rate of detection. This paper presents a deep learning framework consisting of deep neural networks with convolutional layers to facilitate the process of tumor detection, localization, and characterization from scattering parameter measurements and metadata features. The developed deep learning framework outperforms other techniques in the literature in terms of detection accuracy, tumor localization, and characterization. The promising results of this paper demonstrate the potential and benefits of performing BMI via deep neural networks trained on practical scattering parameter measurements.
{"title":"A Deep Learning Framework for Breast Tumor Detection and Localization from Microwave Imaging Data","authors":"Salwa K. Al Khatib, Tarek Naous, R. Shubair, H. M. E. Misilmani","doi":"10.1109/icecs53924.2021.9665521","DOIUrl":"https://doi.org/10.1109/icecs53924.2021.9665521","url":null,"abstract":"Breast Microwave Imaging (BMI) has emerged as a viable alternative to conventional breast cancer screening techniques due to its favorable features and a higher rate of detection. This paper presents a deep learning framework consisting of deep neural networks with convolutional layers to facilitate the process of tumor detection, localization, and characterization from scattering parameter measurements and metadata features. The developed deep learning framework outperforms other techniques in the literature in terms of detection accuracy, tumor localization, and characterization. The promising results of this paper demonstrate the potential and benefits of performing BMI via deep neural networks trained on practical scattering parameter measurements.","PeriodicalId":448558,"journal":{"name":"2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-11-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129203960","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-11-28DOI: 10.1109/icecs53924.2021.9665480
N. Naskas, Nikolaos Alexiou, Spyros Gkardiakos, Aris Agathokleous, Nikos Tsoutsos, Kostas Kontaxis, George Ntounas, Giannis Kousparis
This paper presents a fractional N Phase Locked Loop (PLL) integrated circuit (IC) implemented in 65nm bulk CMOS, targeting mmWave and RADAR applications. The IC is comprised of a PLL with integrated active loop filter and Voltage-Controlled Oscillator (VCO) and auxiliary blocks such as auto-calibration unit, ramp generator, bandgap reference, lock detector and bias circuits. The PLL uses an external reference frequency 40-320MHz and provides a local oscillator (LO) output signal in the range [8.8–9.9]GHz with low phase noise (PN) and output power 0dBm on a 50 Ohm load. The total silicon area is $2.2times 0.76 text{mm}^{2}$ and its power consumption is 270mW from a 1.8V supply.
{"title":"A Low Phase Noise Fractional-N PLL for mmWave Telecom and RADAR Applications","authors":"N. Naskas, Nikolaos Alexiou, Spyros Gkardiakos, Aris Agathokleous, Nikos Tsoutsos, Kostas Kontaxis, George Ntounas, Giannis Kousparis","doi":"10.1109/icecs53924.2021.9665480","DOIUrl":"https://doi.org/10.1109/icecs53924.2021.9665480","url":null,"abstract":"This paper presents a fractional N Phase Locked Loop (PLL) integrated circuit (IC) implemented in 65nm bulk CMOS, targeting mmWave and RADAR applications. The IC is comprised of a PLL with integrated active loop filter and Voltage-Controlled Oscillator (VCO) and auxiliary blocks such as auto-calibration unit, ramp generator, bandgap reference, lock detector and bias circuits. The PLL uses an external reference frequency 40-320MHz and provides a local oscillator (LO) output signal in the range [8.8–9.9]GHz with low phase noise (PN) and output power 0dBm on a 50 Ohm load. The total silicon area is $2.2times 0.76 text{mm}^{2}$ and its power consumption is 270mW from a 1.8V supply.","PeriodicalId":448558,"journal":{"name":"2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-11-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123854347","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-11-28DOI: 10.1109/icecs53924.2021.9665639
Al-Dakheeli Muhammed, Hadeer Essam, Beshoy Alber, Kirolos Samuel, Hagar Muhammed, M. Wagdy, Nouran Khaled, Hadeer Fawzy, Aya Tarek, Mohamed Abdel Salam, M. El-Kharashi
In this paper we present our implementation of a Deep Queue Network (DQN) AI Agent model for car autonomous navigation. The agent is capable of lane keeping without making any collisions with the surrounding vehicle and has learnt to move fast and safe in intersections. The model has been trained using two front camera sensors (depth and segmentation) and a collision detector. We also demonstrate how to connect this agent to functional mockup units (FMUs) to simulate the mechatronics part of the car. The deployment of our model has been demonstrated in a CARLA car simulator environment.
{"title":"Developing AI Agent with Functional Mockup Units for Car Autonomous Navigation","authors":"Al-Dakheeli Muhammed, Hadeer Essam, Beshoy Alber, Kirolos Samuel, Hagar Muhammed, M. Wagdy, Nouran Khaled, Hadeer Fawzy, Aya Tarek, Mohamed Abdel Salam, M. El-Kharashi","doi":"10.1109/icecs53924.2021.9665639","DOIUrl":"https://doi.org/10.1109/icecs53924.2021.9665639","url":null,"abstract":"In this paper we present our implementation of a Deep Queue Network (DQN) AI Agent model for car autonomous navigation. The agent is capable of lane keeping without making any collisions with the surrounding vehicle and has learnt to move fast and safe in intersections. The model has been trained using two front camera sensors (depth and segmentation) and a collision detector. We also demonstrate how to connect this agent to functional mockup units (FMUs) to simulate the mechatronics part of the car. The deployment of our model has been demonstrated in a CARLA car simulator environment.","PeriodicalId":448558,"journal":{"name":"2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-11-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123197309","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-11-28DOI: 10.1109/icecs53924.2021.9665632
Theodoros Panagiotis Chatzinikolaou, Iosif-Angelos Fyrigos, V. Ntinas, Stavros Kitsios, P. Bousoulas, Michail-Antisthenis I. Tsompanas, D. Tsoukalas, A. Adamatzky, G. Sirakoulis
As conventional computing systems are striving to increase their performance in order to compensate for the growing demand of solving difficult problems, emergent and unconventional computing approaches are being developed to provide alternatives on efficiently solving a plethora of those complex problems. Chemical computers which use chemical reactions as their main characteristic can be strong candidates for these new approaches. Oscillating networks of novel nano-devices like memristors are also able to perform calculations with their rich dynamics and their strong memory and computing features. In this work, the combination of the aforementioned approaches is achieved that capitalizes on the threshold switching mechanism of low-voltage CBRAM devices to establish a memristive oscillating circuitry that is able to act as a chemical reaction - diffusion system through the network nodes' interactions. The propagation of the voltage signals throughout the medium can be used to establish a mechanism for specific logic operations according to the desired logic function leading to the nano-implementation of Margolus chemical wave logic gate.
{"title":"Margolus Chemical Wave Logic Gate with Memristive Oscillatory Networks","authors":"Theodoros Panagiotis Chatzinikolaou, Iosif-Angelos Fyrigos, V. Ntinas, Stavros Kitsios, P. Bousoulas, Michail-Antisthenis I. Tsompanas, D. Tsoukalas, A. Adamatzky, G. Sirakoulis","doi":"10.1109/icecs53924.2021.9665632","DOIUrl":"https://doi.org/10.1109/icecs53924.2021.9665632","url":null,"abstract":"As conventional computing systems are striving to increase their performance in order to compensate for the growing demand of solving difficult problems, emergent and unconventional computing approaches are being developed to provide alternatives on efficiently solving a plethora of those complex problems. Chemical computers which use chemical reactions as their main characteristic can be strong candidates for these new approaches. Oscillating networks of novel nano-devices like memristors are also able to perform calculations with their rich dynamics and their strong memory and computing features. In this work, the combination of the aforementioned approaches is achieved that capitalizes on the threshold switching mechanism of low-voltage CBRAM devices to establish a memristive oscillating circuitry that is able to act as a chemical reaction - diffusion system through the network nodes' interactions. The propagation of the voltage signals throughout the medium can be used to establish a mechanism for specific logic operations according to the desired logic function leading to the nano-implementation of Margolus chemical wave logic gate.","PeriodicalId":448558,"journal":{"name":"2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-11-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123603592","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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