Asymmetric large size multiplication using embedded blocks with efficient compression technique in FPGAs

Abstract

In this paper, asymmetric non-pipelined large size unsigned multipliers are implemented using symmetric and asymmetric embedded multipliers in FPGAs. The decomposition of the operands used in this approach is based on the sizes of the embedded blocks. The partial products of the segmented operands are organized in rows, and the additions of the products are performed through optimized compression dictated by the architecture of the CLB. The optimization algorithm has led to the minimization of the total critical path delay with reduced utilization of FPGA embedded blocks. The multipliers are implemented in Xilinx' FPGAs using 18×18-bit and 25×18-bit embedded signed multipliers. The implementation results have demonstrated the effectiveness of the proposed approach achieving speed improvement of 29% and reduction of embedded block utilization of 28% for operand size of up to 192 bits compared to the Standard scheme.