Pub Date : 2011-12-11DOI: 10.1109/ICECS.2011.6122260
S. Sahnoun, A. Fakhfakh, N. Masmoudi, H. Levi
Today, design requirements are extending more and more from electronic (analogue and digital) to multidiscipline ones. These current needs imply implementation of methodologies to make the CAD product reliable in order to improve time to market, study costs, reusability and reliability of the design process. This paper proposes a high level design approach applied for the characterization and the optimization of fractional-N synthesizer acting as a direct GPSK modulator and designed for the UMTS standard application. It uses the hardware description language VHDL-AMS and a genetic algorithm to optimize the modulator with a considerably reduced CPU time before passing to a transistor level characterization.
{"title":"High level characterization and optimization of a GPSK modulator with genetic algorithm","authors":"S. Sahnoun, A. Fakhfakh, N. Masmoudi, H. Levi","doi":"10.1109/ICECS.2011.6122260","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122260","url":null,"abstract":"Today, design requirements are extending more and more from electronic (analogue and digital) to multidiscipline ones. These current needs imply implementation of methodologies to make the CAD product reliable in order to improve time to market, study costs, reusability and reliability of the design process. This paper proposes a high level design approach applied for the characterization and the optimization of fractional-N synthesizer acting as a direct GPSK modulator and designed for the UMTS standard application. It uses the hardware description language VHDL-AMS and a genetic algorithm to optimize the modulator with a considerably reduced CPU time before passing to a transistor level characterization.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125629105","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-11DOI: 10.1109/ICECS.2011.6122360
K. Baraka, E. Kerhervé, J. Pham, M. E. Hassan
This work presents the feasibility of a new method to reconfigure Bulk Acoustic Wave-Solidly Mounted Resonator (BAW-SMR) filters by adding capacitors in series with transistors to the shunt resonators and by controlling these transistors with a 2to4 decoder. This method is applied to filters operating in the W-CDMA (2.11–2.17 GHz) communication standard. Experimental results show a tuning range of 14MHz, whereas 12MHz of tuning range was achieved in the simulation.
{"title":"Controlling the bandwidth of Bulk Acoustic Wave filter using a decoder designed on 65nm process","authors":"K. Baraka, E. Kerhervé, J. Pham, M. E. Hassan","doi":"10.1109/ICECS.2011.6122360","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122360","url":null,"abstract":"This work presents the feasibility of a new method to reconfigure Bulk Acoustic Wave-Solidly Mounted Resonator (BAW-SMR) filters by adding capacitors in series with transistors to the shunt resonators and by controlling these transistors with a 2to4 decoder. This method is applied to filters operating in the W-CDMA (2.11–2.17 GHz) communication standard. Experimental results show a tuning range of 14MHz, whereas 12MHz of tuning range was achieved in the simulation.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124033878","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-01DOI: 10.1109/ICECS.2011.6122315
Hawraa Amhaz, Hassan Abbass, H. Zimouche, G. Sicard
In this paper we present an improved version of the readout technique proposed in [7]. It concerns a continuous operating logarithmic image sensor with 120dB of Dynamic Range (DR). The pixel element presents also improved characteristics, compared to the standard logarithmic pixel, especially in terms of Fixed Pattern Noise compensation and extended output voltage swing. The first goal of this readout technique is to reduce the data temporal redundancies in order to reduce the dataflow outgoing from the sensor. The main idea lies in the distribution of the sensor into macro-pixels composed of nxn pixel elements. Each macro-pixel generates the mean value of all its pixels luminosities, and then an event detector is used to detect any variation in this mean value. A positive reaction of this event detector triggers the readout of the block pixel elements. The Matlab emulation results show the intended dataflow reduction rate. The pixel schematic and layout designed in the CMOS 0.35μm AMS technology, the event detector architecture and the bloc diagram of the system are detailed later through the different sections of this paper.
{"title":"An improved smart readout technique based on temporal redundancies suppression designed for logarithmic CMOS image sensor","authors":"Hawraa Amhaz, Hassan Abbass, H. Zimouche, G. Sicard","doi":"10.1109/ICECS.2011.6122315","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122315","url":null,"abstract":"In this paper we present an improved version of the readout technique proposed in [7]. It concerns a continuous operating logarithmic image sensor with 120dB of Dynamic Range (DR). The pixel element presents also improved characteristics, compared to the standard logarithmic pixel, especially in terms of Fixed Pattern Noise compensation and extended output voltage swing. The first goal of this readout technique is to reduce the data temporal redundancies in order to reduce the dataflow outgoing from the sensor. The main idea lies in the distribution of the sensor into macro-pixels composed of nxn pixel elements. Each macro-pixel generates the mean value of all its pixels luminosities, and then an event detector is used to detect any variation in this mean value. A positive reaction of this event detector triggers the readout of the block pixel elements. The Matlab emulation results show the intended dataflow reduction rate. The pixel schematic and layout designed in the CMOS 0.35μm AMS technology, the event detector architecture and the bloc diagram of the system are detailed later through the different sections of this paper.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115008395","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-01DOI: 10.1109/ICECS.2011.6122252
Xueqing Li, Qi Wei, Huazhong Yang
This paper proposes a novel complementary current approach to eliminating the code-dependence in the output impedance of current-steering digital-to-analog converters (DACs), and increasing the spurious-free dynamic range (SFDR) significantly. A 14bit 1.0GS/s current-steering DAC design example shows an SFDR increase of 10∼15dB. In traditional designs, one major effect that degrades the linearity is the code-dependence of the DAC's output impedance, which becomes a bottleneck at high frequencies because of the parasitic capacitance in the current branches. By adding additional current sources and switches to keep the DAC's output impedance nearly constant at different digital input codes, the proposed approach increases the DAC's SFDR by tens of dBs.
{"title":"Code-independent output impedance: A new approach to increasing the linearity of current-steering DACs","authors":"Xueqing Li, Qi Wei, Huazhong Yang","doi":"10.1109/ICECS.2011.6122252","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122252","url":null,"abstract":"This paper proposes a novel complementary current approach to eliminating the code-dependence in the output impedance of current-steering digital-to-analog converters (DACs), and increasing the spurious-free dynamic range (SFDR) significantly. A 14bit 1.0GS/s current-steering DAC design example shows an SFDR increase of 10∼15dB. In traditional designs, one major effect that degrades the linearity is the code-dependence of the DAC's output impedance, which becomes a bottleneck at high frequencies because of the parasitic capacitance in the current branches. By adding additional current sources and switches to keep the DAC's output impedance nearly constant at different digital input codes, the proposed approach increases the DAC's SFDR by tens of dBs.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115224742","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-01DOI: 10.1109/ICECS.2011.6122269
J. Carmo, R. Rocha, Manuel F. Silva, D. S. Ferreira, J. Ribeiro, J. Correia
This paper presents a low-cost technology for fabricating optical filters arrays tuned for the primary colors. The fabrication process presented in this paper is intended for directly printing the optical filters into a transparent flexible substrate (acetate). The target application of these optical filters is for enabling the acquisition of multicolor stereoscopic images with a sensor made in CMOS technology.
{"title":"Stereoscopic image sensor with low-cost RGB filters tunned for the visible range","authors":"J. Carmo, R. Rocha, Manuel F. Silva, D. S. Ferreira, J. Ribeiro, J. Correia","doi":"10.1109/ICECS.2011.6122269","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122269","url":null,"abstract":"This paper presents a low-cost technology for fabricating optical filters arrays tuned for the primary colors. The fabrication process presented in this paper is intended for directly printing the optical filters into a transparent flexible substrate (acetate). The target application of these optical filters is for enabling the acquisition of multicolor stereoscopic images with a sensor made in CMOS technology.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"130 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115688779","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-01DOI: 10.1109/ICECS.2011.6122358
P. Harikumar, A. K. M. Pillai, J. Wikner
Pipelined analog-to-digital converters (ADCs) achieve low to moderate resolutions at high bandwidths while sigma-delta (ΣΔ) ADCs provide high resolution at moderate bandwidths. A switched-capacitor (SC) block which can function as an integrator or an MDAC can be used to implement a reconfigurable ADC (R-ADC) which supports both these types of architectures. Through the use of high level models this work attempts to derive the capacitance and critical opamp parameters such as DC gain and bandwidth of the SC blocks in a reconfigurable ADC. Scaling of capacitance afforded by the noise shaping property of ΣΔ loops as well as the inter-stage gain of pipelined ADCs is used to minimize the total capacitance. This work can be used as reference material to understand some of the design trade-offs in R-ADCs.
{"title":"A study on switched-capacitor blocks for reconfigurable ADCs","authors":"P. Harikumar, A. K. M. Pillai, J. Wikner","doi":"10.1109/ICECS.2011.6122358","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122358","url":null,"abstract":"Pipelined analog-to-digital converters (ADCs) achieve low to moderate resolutions at high bandwidths while sigma-delta (ΣΔ) ADCs provide high resolution at moderate bandwidths. A switched-capacitor (SC) block which can function as an integrator or an MDAC can be used to implement a reconfigurable ADC (R-ADC) which supports both these types of architectures. Through the use of high level models this work attempts to derive the capacitance and critical opamp parameters such as DC gain and bandwidth of the SC blocks in a reconfigurable ADC. Scaling of capacitance afforded by the noise shaping property of ΣΔ loops as well as the inter-stage gain of pipelined ADCs is used to minimize the total capacitance. This work can be used as reference material to understand some of the design trade-offs in R-ADCs.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116704731","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-01DOI: 10.1109/ICECS.2011.6122238
I. Basith, Tareq Muhammad Supon, Ajit Muhury, R. Rashidzadeh, M. Ahmadi
The focus of this paper is to study the reliability issue of single-electron tunneling (SET) technology using multi-island structure for 1-bit full adder circuit. A new set of parameters are proposed in this paper showing better sensitivity towards the random background charge (RBC). Impact of temperature and background charge on the performance parameters and voltage swing are also analyzed. Multi-island clique (K-3) structure is implemented and compared with the designs reported in the literature.
{"title":"Performance enhancement of single electron junction 1-bit full adder","authors":"I. Basith, Tareq Muhammad Supon, Ajit Muhury, R. Rashidzadeh, M. Ahmadi","doi":"10.1109/ICECS.2011.6122238","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122238","url":null,"abstract":"The focus of this paper is to study the reliability issue of single-electron tunneling (SET) technology using multi-island structure for 1-bit full adder circuit. A new set of parameters are proposed in this paper showing better sensitivity towards the random background charge (RBC). Impact of temperature and background charge on the performance parameters and voltage swing are also analyzed. Multi-island clique (K-3) structure is implemented and compared with the designs reported in the literature.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125560843","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-01DOI: 10.1109/ICECS.2011.6122393
Sajjad Moshfe, A. Khoei, K. Hadidi
This paper presents a fully programmable compact analog CMOS realization of triangular/trapezoidal/z-shaped/s-shaped membership functions generator circuit in current mode approach. Analog realization of the programming units distinct the circuit from the previous works in power consumption, accuracy, speed, and continually parameters changing. Designed circuit was simulated by HSPICE simulator with level 49 parameters (BSIM3v3) and the simulation results verified the performance of the proposed fuzzifier. Finally, the presented layout of the fuzzifier shows it occupies less than 0.01mm2.
{"title":"A highly accurate fully programmable fuzzifier in current mode approach","authors":"Sajjad Moshfe, A. Khoei, K. Hadidi","doi":"10.1109/ICECS.2011.6122393","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122393","url":null,"abstract":"This paper presents a fully programmable compact analog CMOS realization of triangular/trapezoidal/z-shaped/s-shaped membership functions generator circuit in current mode approach. Analog realization of the programming units distinct the circuit from the previous works in power consumption, accuracy, speed, and continually parameters changing. Designed circuit was simulated by HSPICE simulator with level 49 parameters (BSIM3v3) and the simulation results verified the performance of the proposed fuzzifier. Finally, the presented layout of the fuzzifier shows it occupies less than 0.01mm2.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"109 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114921209","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-01DOI: 10.1109/ICECS.2011.6122357
Walid Bouallegue, Salma Bouslama Bouabdallah, M. Tagina
In this paper, a new adaptive fuzzy Fault Detection and Isolation (FDI) approach of non linear Bond Graph (BG) uncertain parameters systems is proposed. In this approach two methods are combined: adaptive thresholds based method and a fuzzy logic method. A simulation example of a real system is provided to show the efficiency of the proposed method in comparison to to adaptive thresholds based method.
{"title":"A new adaptive fuzzy FDI method for Bond Graph uncertain parameters systems","authors":"Walid Bouallegue, Salma Bouslama Bouabdallah, M. Tagina","doi":"10.1109/ICECS.2011.6122357","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122357","url":null,"abstract":"In this paper, a new adaptive fuzzy Fault Detection and Isolation (FDI) approach of non linear Bond Graph (BG) uncertain parameters systems is proposed. In this approach two methods are combined: adaptive thresholds based method and a fuzzy logic method. A simulation example of a real system is provided to show the efficiency of the proposed method in comparison to to adaptive thresholds based method.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114420332","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-01DOI: 10.1109/ICECS.2011.6122378
Martin Dubois, M. Boukadoum
As processors on-chip gain in numbers and complexity, task scheduling has become an important concern in system design, and the related research has produced substantial and diversified knowledge. As a result, the efficient taping and management of this knowledge has become a concern in itself. In particular, it can bring new ways to improve scheduling algorithms. This paper describes a new algorithm class based on association rules mining. It serves to both increase the knowledge about a particular scheduling algorithm and show how to improve its performance. Two examples show how this new methodology can be used to improve makespan and processor use globally by optimizing the scheduling method locally.
{"title":"Rules class approach to scheduling algorithms","authors":"Martin Dubois, M. Boukadoum","doi":"10.1109/ICECS.2011.6122378","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122378","url":null,"abstract":"As processors on-chip gain in numbers and complexity, task scheduling has become an important concern in system design, and the related research has produced substantial and diversified knowledge. As a result, the efficient taping and management of this knowledge has become a concern in itself. In particular, it can bring new ways to improve scheduling algorithms. This paper describes a new algorithm class based on association rules mining. It serves to both increase the knowledge about a particular scheduling algorithm and show how to improve its performance. Two examples show how this new methodology can be used to improve makespan and processor use globally by optimizing the scheduling method locally.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128587314","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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