A. Rodríguez-Pérez, J. Ruiz-Amaya, Oscar Guerra, M. Delgado-Restituto
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引用次数: 4
Abstract
This paper describes the architecture of a neural spike recording channel with feature extraction capabilities and presents the design of one of its key elements, a reconfigurable 8-bit ADC. The ADC can be programmed for different conversion rates and embeds a 0–18dB programmable gain amplifier with discrete gain steps of 3dB. Simulation results from extracted layout of the ADC, designed in a 130nm CMOS technology, obtain almost 8-bit ENOB at 22.2kS/s and 90kS/s, with a power consumption of 500nW and 1.8μW, respectively.
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