Machine Learning Approach for Mixed type Wafer Defect Pattern Recognition by ResNet Architecture

Abstract

Semiconductor manufacturing process involves various steps: fabrication of Wafers, testing of wafers, assembly of each single die and package level final test. Out of which, testing of wafer for defect detection and classification is the most important step where defective dies are eliminated. This improves the efficiency of the overall manufacturing process. Semiconductor wafer defects can be basic defects or mixed defects containing two or more basic defects. Since these defects varied from wafer to wafer and are complex, the accuracy obtained from traditional deep learning model is poor. To address this problem, a semiconductor mixed defect pattern recognition based on Residual Network (ResNet) Architecture is attempted. Among the ResNet architectures, ResNet50 is selected for wafer defect pattern recognition which has a 50 layer structure. The model is evaluated based on data set with 15 mixed defect patterns which were generated from WM-811K wafer map data set. Training, testing and validation of the data set is done. The performance parameters are generated and compared the performance with four different architectures including Convolutional Neural Network(CNN). The training results indicate that the ResNet50 shows a better performance in terms of accuracy, precision, recall and F1 score.