A programmable processing element dedicated as building block for a large area integrated multiprocessor system

1996 Proceedings. Eighth Annual IEEE International Conference on Innovative Systems in Silicon Pub Date : 1996-10-09 DOI:10.1109/ICISS.1996.552416

K. Hermann, J. Hilgenstock, K. Gaedke, H. Jeschke, P. Pirsch

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引用次数: 3

Abstract

The architecture and implementation of a programmable processing element dedicated as building block for a large area integrated multiprocessor system is presented. The processor element allows an efficient implementation of video coding standards. It consists of a RISC processor supplemented by a low level coprocessor for computation intensive convolution-like tasks. Several of the processing elements can be bus-connected to built a coarse-grained MIMD based large area integrated multiprocessor system. Each of the processor elements provides high performance for video coding tasks in order to keep the overall number of required processing elements for complex real-time video coding applications small. A key feature of the processing element to support large area integration is a unidirectional data supply which allows reconfiguration strategies for the interconnection network. Furthermore on-chip program and data memories have been implemented in order to relax the overall bandwidth requirements of the large area integrated multiprocessor system.

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用于大面积集成多处理器系统的可编程处理元件

介绍了一种专用于大面积集成多处理器系统的可编程处理单元的体系结构和实现方法。处理器元素允许有效地实现视频编码标准。它由一个RISC处理器和一个低级协处理器组成，用于类似卷积的计算密集型任务。几个处理元件可以通过总线连接来构建基于粗粒度MIMD的大面积集成多处理器系统。每个处理器元素都为视频编码任务提供高性能，以保持复杂实时视频编码应用所需处理元素的总数较小。支持大面积集成的处理元件的一个关键特征是单向数据供应，它允许互连网络的重新配置策略。此外，为了降低大面积集成多处理器系统的总体带宽要求，还实现了片上程序和数据存储器。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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1996 Proceedings. Eighth Annual IEEE International Conference on Innovative Systems in Silicon

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