{"title":"Survey of low power techniques for VLSI design","authors":"E. de Angel, E. Swartzlander","doi":"10.1109/ICISS.1996.552423","DOIUrl":null,"url":null,"abstract":"This paper presents a survey of low power techniques for digital circuits. The techniques presented in this paper have been implemented in modified-Booth multipliers. The multipliers have been designed in 0.6 /spl mu/m technology and simulated in PowerMill.","PeriodicalId":131620,"journal":{"name":"1996 Proceedings. Eighth Annual IEEE International Conference on Innovative Systems in Silicon","volume":"9 5","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1996-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"1996 Proceedings. Eighth Annual IEEE International Conference on Innovative Systems in Silicon","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICISS.1996.552423","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 10
Abstract
This paper presents a survey of low power techniques for digital circuits. The techniques presented in this paper have been implemented in modified-Booth multipliers. The multipliers have been designed in 0.6 /spl mu/m technology and simulated in PowerMill.
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