Design of a high speed and low power digital matched filter for CDMA system

I. Saini, R. Sarin, M. Khosla, H. Singh
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引用次数: 2

Abstract

Code division multiple access (CDMA) is a rapidly expanding data transmission technique in the emerging universal mobile telecommunication system. Digital matched filter (DMF) in a CDMA system is used for correlating the received data with the transmitted data. The key issues in the design of a DMF are speed and power. This paper presents the design of a fine-grain pipelined DMF with clock gating with an objective to increase the speed and at the same time reduce the power consumption. The design has been verified through simulation and synthesis of the existing DMF and the proposed architectures. Verilog HDL coding of the design is done using Xilinx ISE design tool. Speed and estimated power consumption of the design are obtained using XST Synthesis and XPower tools of Xilinx respectively.
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CDMA系统中高速低功耗数字匹配滤波器的设计
码分多址(CDMA)是在新兴的通用移动通信系统中迅速发展起来的数据传输技术。在CDMA系统中,数字匹配滤波器(DMF)用于将接收数据与发送数据相关联。DMF设计的关键问题是速度和功率。本文提出了一种带时钟门控的细粒度流水线DMF的设计,目的是在提高速度的同时降低功耗。通过对现有DMF和所提架构的仿真和综合,验证了该设计。设计的Verilog HDL编码使用赛灵思ISE设计工具完成。使用Xilinx的XST Synthesis和XPower工具分别获得了设计的速度和估计功耗。
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