Weihong Gao, JeongHee Kim, Hsiao-Chi Peng, C. Huang, O. Patterson, yu-chi Su, Hsiang-Ting Yeh, Sean Starr-baier, Haokun Hu
{"title":"Rapid In-line Process Window Characterization Using Voltage Contrast Test Structures for Advanced FinFET Technology Development","authors":"Weihong Gao, JeongHee Kim, Hsiao-Chi Peng, C. Huang, O. Patterson, yu-chi Su, Hsiang-Ting Yeh, Sean Starr-baier, Haokun Hu","doi":"10.1109/ASMC.2019.8791785","DOIUrl":null,"url":null,"abstract":"A methodology for rapid process window characterization using families of voltage contrast (VC) test structures is described. While VC test structures have been in common use in the semiconductor industry for targeted applications for twenty years, we propose comprehensive application of VC test structures as a powerful tool for greatly accelerating semiconductor technology development. Test chips may be developed covering essentially all possible failure mechanisms. These chips include families of structures for monitoring both the critical process windows and the nominal failure rate. These structures are inspected in-line thereby providing the earliest possible feedback for split experiment evaluation, yield projection, and excursion detection. This paper reports on the application of this methodology to an advanced FinFET technology. Best methods for test structure layout, inspection setup, and binning strategy and reporting are described. Selected test structure designs and results are presented to illustrate these principles.","PeriodicalId":287541,"journal":{"name":"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"493 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASMC.2019.8791785","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
A methodology for rapid process window characterization using families of voltage contrast (VC) test structures is described. While VC test structures have been in common use in the semiconductor industry for targeted applications for twenty years, we propose comprehensive application of VC test structures as a powerful tool for greatly accelerating semiconductor technology development. Test chips may be developed covering essentially all possible failure mechanisms. These chips include families of structures for monitoring both the critical process windows and the nominal failure rate. These structures are inspected in-line thereby providing the earliest possible feedback for split experiment evaluation, yield projection, and excursion detection. This paper reports on the application of this methodology to an advanced FinFET technology. Best methods for test structure layout, inspection setup, and binning strategy and reporting are described. Selected test structure designs and results are presented to illustrate these principles.