Pub Date : 2019-05-06DOI: 10.1109/ASMC.2019.8791777
Árpád Jakab, J. Byrnes, László Makai, A. Engelsberg, A. Findlay, A. Vaid, Nicholas Pieniazek, J. Barker, Jeff Wood, Péter Rutka, P. Basa, Jack Downey
A novel optical reflectometry solution, capable of measuring planar, blanket thin films on 300mm Si wafers within a self-contained and portable Front Opening Unified Pod (FOUP)-based compact metrology system, the Metrology- FOUP (M-FOUP) System, is introduced. Key applications of the new instrument are presented by demonstrating measurement of unpatterned film thickness on samples representing typical daily qualification of process equipment. Benchmark data on characteristic samples from semiconductor production fab are presented, together with comparing the test results to that measured by conventional (stand-alone) metrology tools.
{"title":"Integration of Reflectometry into a FOUP for Improved Cycle Time","authors":"Árpád Jakab, J. Byrnes, László Makai, A. Engelsberg, A. Findlay, A. Vaid, Nicholas Pieniazek, J. Barker, Jeff Wood, Péter Rutka, P. Basa, Jack Downey","doi":"10.1109/ASMC.2019.8791777","DOIUrl":"https://doi.org/10.1109/ASMC.2019.8791777","url":null,"abstract":"A novel optical reflectometry solution, capable of measuring planar, blanket thin films on 300mm Si wafers within a self-contained and portable Front Opening Unified Pod (FOUP)-based compact metrology system, the Metrology- FOUP (M-FOUP) System, is introduced. Key applications of the new instrument are presented by demonstrating measurement of unpatterned film thickness on samples representing typical daily qualification of process equipment. Benchmark data on characteristic samples from semiconductor production fab are presented, together with comparing the test results to that measured by conventional (stand-alone) metrology tools.","PeriodicalId":287541,"journal":{"name":"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127152695","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-06DOI: 10.1109/ASMC.2019.8791758
Karl-Benedikt Reith, P. Boden, Martin Däumler, S. Rank, T. Schmidt, Ralf Hupfer
Using a fleet of automated guided vehicles (AGV) is an increasingly popular option for a transportation system in semiconductor fabrication plants (fab), where AGVs can either serve as a supplement to the already existing transport system or as a first step towards the automation of transports. AGV systems have a high number of design choices, which need to be taken into consideration when planning and operating such systems in a fab. In addition, the combination of various AGV system characteristics has effects on the system performance that are difficult to predict. In this publication important aspects and dependencies are outlined regarding major AGV system characteristics like layout topologies and minor system characteristics like vehicle handling time or vehicle velocity.
{"title":"Evaluating Automated Guided Vehicle System Characteristics in Semiconductor Fab Automated Material Handling Systems","authors":"Karl-Benedikt Reith, P. Boden, Martin Däumler, S. Rank, T. Schmidt, Ralf Hupfer","doi":"10.1109/ASMC.2019.8791758","DOIUrl":"https://doi.org/10.1109/ASMC.2019.8791758","url":null,"abstract":"Using a fleet of automated guided vehicles (AGV) is an increasingly popular option for a transportation system in semiconductor fabrication plants (fab), where AGVs can either serve as a supplement to the already existing transport system or as a first step towards the automation of transports. AGV systems have a high number of design choices, which need to be taken into consideration when planning and operating such systems in a fab. In addition, the combination of various AGV system characteristics has effects on the system performance that are difficult to predict. In this publication important aspects and dependencies are outlined regarding major AGV system characteristics like layout topologies and minor system characteristics like vehicle handling time or vehicle velocity.","PeriodicalId":287541,"journal":{"name":"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"379 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124727027","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-06DOI: 10.1109/ASMC.2019.8791796
SM Guo, Jx Liu, R. Navalakhe, A. Lee, B. Tsai, Mahatma Lin, M. Plihal, Jianyun Zhou
For inline defect inspection it is important to achieve a high capture rate of defects of interest (DOI) at low nuisance rate to increase production efficiency. A broadband plasma (BBP) wafer defect inspection system with Inline Defect Organizer™ (iDO) can separate DOI and nuisance defects into different bins.However, high expertise is required to set up an effective iDO™ classifier. Traditional iDO setup complexity increases as design rules shrink. A novel approach is developed by adopting machine learning algorithms and SEM-classified defect data to create a new iDO classifier (a.k.a. iDO 2.0). The results are promising, showing that iDO 2.0 classifier outperforms the iDO in sensitivity, nuisance rate, ease of use, time to results and cross- device portability.
{"title":"Inline Inspection Improvement using Machine Learning on Broadband Plasma Inspector in an Advanced Foundry Fab","authors":"SM Guo, Jx Liu, R. Navalakhe, A. Lee, B. Tsai, Mahatma Lin, M. Plihal, Jianyun Zhou","doi":"10.1109/ASMC.2019.8791796","DOIUrl":"https://doi.org/10.1109/ASMC.2019.8791796","url":null,"abstract":"For inline defect inspection it is important to achieve a high capture rate of defects of interest (DOI) at low nuisance rate to increase production efficiency. A broadband plasma (BBP) wafer defect inspection system with Inline Defect Organizer™ (iDO) can separate DOI and nuisance defects into different bins.However, high expertise is required to set up an effective iDO™ classifier. Traditional iDO setup complexity increases as design rules shrink. A novel approach is developed by adopting machine learning algorithms and SEM-classified defect data to create a new iDO classifier (a.k.a. iDO 2.0). The results are promising, showing that iDO 2.0 classifier outperforms the iDO in sensitivity, nuisance rate, ease of use, time to results and cross- device portability.","PeriodicalId":287541,"journal":{"name":"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130840378","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-06DOI: 10.1109/ASMC.2019.8791756
A. Zhakov, Hailong Zhu, Armin Siegel, S. Rank, T. Schmidt, Lars Fienhold, S. Hummel
In order to ensure safe and fast transportation of wafers in 300 mm semiconductor factories, overhead transport systems (OHT) are primarily used. These systems consist of a rail network and vehicles. To avoid congestion and delays in production, high availability of individual rail sections is essential. In order to ensure this, normally extensive preventive maintenance is required. In this article, we focus on automatic checks for faults of the rail network by capturing an area of the rail with optical sensors. Our objective is the identification of faults in real time. We considered the identification with a basic determining approach as well as the application of artificial neural networks (ANN). Due to the lack of fixed rules designing an ANN we tested different topologies for our application. As a result, our ANN provides accurate real time fault detection which allows a needs-based, resource-saving and efficient maintenance procedure for 24/7 semiconductor manufacturing.
{"title":"Automatic Fault Detection in Rails of Overhead Transport Systems for Semiconductor Fabs","authors":"A. Zhakov, Hailong Zhu, Armin Siegel, S. Rank, T. Schmidt, Lars Fienhold, S. Hummel","doi":"10.1109/ASMC.2019.8791756","DOIUrl":"https://doi.org/10.1109/ASMC.2019.8791756","url":null,"abstract":"In order to ensure safe and fast transportation of wafers in 300 mm semiconductor factories, overhead transport systems (OHT) are primarily used. These systems consist of a rail network and vehicles. To avoid congestion and delays in production, high availability of individual rail sections is essential. In order to ensure this, normally extensive preventive maintenance is required. In this article, we focus on automatic checks for faults of the rail network by capturing an area of the rail with optical sensors. Our objective is the identification of faults in real time. We considered the identification with a basic determining approach as well as the application of artificial neural networks (ANN). Due to the lack of fixed rules designing an ANN we tested different topologies for our application. As a result, our ANN provides accurate real time fault detection which allows a needs-based, resource-saving and efficient maintenance procedure for 24/7 semiconductor manufacturing.","PeriodicalId":287541,"journal":{"name":"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126241082","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-06DOI: 10.1109/ASMC.2019.8791749
E. Gebreselasie, A. Loiseau, Y. Ngu, Ian Mcallum-Cook
0.35um SiGe BiCMOS wafers were fabricated using Ti, Co, Pt, and Ni salicide processes optimized for a range of CMOS technology nodes down to 90nm. On-wafer circuitry was used to program discrete eFuse elements to compare their pre and post programmed resistances and behavior during programming between each salicide process employed, with TEM analysis to confirm successful electromigration in the fuse link. Discrete eFuses were also subjected to 100ns Transmission Line Pulse (TLP) to compare ESD handling and robustness, and the associated MOSFET circuitry characterized for safe operating area (SOA) under DC and pulsed conditions. This work demonstrates the compatibility of eFuse technology across a range of process technology nodes, as well as its robustness in high reliability applications.
{"title":"Impact of silicide process on eFuse programming, reliability and ruggedness in RF BiCMOS Technology","authors":"E. Gebreselasie, A. Loiseau, Y. Ngu, Ian Mcallum-Cook","doi":"10.1109/ASMC.2019.8791749","DOIUrl":"https://doi.org/10.1109/ASMC.2019.8791749","url":null,"abstract":"0.35um SiGe BiCMOS wafers were fabricated using Ti, Co, Pt, and Ni salicide processes optimized for a range of CMOS technology nodes down to 90nm. On-wafer circuitry was used to program discrete eFuse elements to compare their pre and post programmed resistances and behavior during programming between each salicide process employed, with TEM analysis to confirm successful electromigration in the fuse link. Discrete eFuses were also subjected to 100ns Transmission Line Pulse (TLP) to compare ESD handling and robustness, and the associated MOSFET circuitry characterized for safe operating area (SOA) under DC and pulsed conditions. This work demonstrates the compatibility of eFuse technology across a range of process technology nodes, as well as its robustness in high reliability applications.","PeriodicalId":287541,"journal":{"name":"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124885713","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-06DOI: 10.1109/ASMC.2019.8791788
E. Ramanathan, Lei Jiang, Q. Takmeel, Silvestre MaryClaire, AnbuSelvam KM Mahalingam, Somnath Ghosh, K. Donegan, A. Chandrasekar, Sunil K. Singh, Henrik Johanson, D. Damjanovic, Zhiguo Sun, A. Sircar, S. Eah, Colin Bombardier, A. daSilva, Brendan O'Brien, A. Roux, B. Cucci, Ordonio Christopher, C. Montgomery, Vandana Venkatasubramanian, Vijaya Rana, J. Mody, J. Shepard, C. Child, B. Morganfeld, Rebekah Sheraw
As technology scaling continues, the selection of materials for sacrificial hard masks become very critical. Sacrificial hard masks are thin films that are used for patterning or protecting critical underlying films from damage during various processes like etching, deposition or planarization. In this article, we discuss the effect of the sacrificial hard mask material on the erosion in the self-aligned via (SAV) patterning process, selectivity in the etch process, adhesion, defectivity, and metallization.
{"title":"Impact of Sacrificial Hard Mask Material in BEOL Integration in Advanced Technology","authors":"E. Ramanathan, Lei Jiang, Q. Takmeel, Silvestre MaryClaire, AnbuSelvam KM Mahalingam, Somnath Ghosh, K. Donegan, A. Chandrasekar, Sunil K. Singh, Henrik Johanson, D. Damjanovic, Zhiguo Sun, A. Sircar, S. Eah, Colin Bombardier, A. daSilva, Brendan O'Brien, A. Roux, B. Cucci, Ordonio Christopher, C. Montgomery, Vandana Venkatasubramanian, Vijaya Rana, J. Mody, J. Shepard, C. Child, B. Morganfeld, Rebekah Sheraw","doi":"10.1109/ASMC.2019.8791788","DOIUrl":"https://doi.org/10.1109/ASMC.2019.8791788","url":null,"abstract":"As technology scaling continues, the selection of materials for sacrificial hard masks become very critical. Sacrificial hard masks are thin films that are used for patterning or protecting critical underlying films from damage during various processes like etching, deposition or planarization. In this article, we discuss the effect of the sacrificial hard mask material on the erosion in the self-aligned via (SAV) patterning process, selectivity in the etch process, adhesion, defectivity, and metallization.","PeriodicalId":287541,"journal":{"name":"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128977604","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-06DOI: 10.1109/ASMC.2019.8791787
Verna Chang Chien, Chi‐Ming Yang, Chi-Chang Hu
Traditionally, wafer cleaning via the batch type in semiconductor manufacturing has been used for many years. And the single wafer processor has developed for the advantage in particle control by preventing the pollution from accumulated materials. Although single wafer processor can overcome the particle and defect problem in conventional wet station, silicon nitride removal by phosphoric acid still uses the bench type tool even other processes including RCA cleaning has been changed to the single wafer tool in advanced technology. One of the reasons is the selectivity of silicon nitride to oxide. In this work, fundamental studies on the etching rate, uniformity, and selectivity were investigated by a general process tuning knobs in the single wafer processor, such as the rotation speed, puddle time, temperature, etc., which brought us a deeper understanding on the relationship of silicon nitride etching rate to the phosphoric acid.
{"title":"The Etching of Silicon Nitride in Phosphoric Acid with Novel Single Wafer Processor","authors":"Verna Chang Chien, Chi‐Ming Yang, Chi-Chang Hu","doi":"10.1109/ASMC.2019.8791787","DOIUrl":"https://doi.org/10.1109/ASMC.2019.8791787","url":null,"abstract":"Traditionally, wafer cleaning via the batch type in semiconductor manufacturing has been used for many years. And the single wafer processor has developed for the advantage in particle control by preventing the pollution from accumulated materials. Although single wafer processor can overcome the particle and defect problem in conventional wet station, silicon nitride removal by phosphoric acid still uses the bench type tool even other processes including RCA cleaning has been changed to the single wafer tool in advanced technology. One of the reasons is the selectivity of silicon nitride to oxide. In this work, fundamental studies on the etching rate, uniformity, and selectivity were investigated by a general process tuning knobs in the single wafer processor, such as the rotation speed, puddle time, temperature, etc., which brought us a deeper understanding on the relationship of silicon nitride etching rate to the phosphoric acid.","PeriodicalId":287541,"journal":{"name":"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116704239","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-06DOI: 10.1109/ASMC.2019.8791745
Y.M. Lu, J.W. Huang, K. Hsiao, Joe Chen, Alex T. Cheng
With shrinking design rules, detecting tiny defects of interest (DOI) is becoming more challenging for wafer inspection tools. Using design-based care areas for inspection systems to characterize DOI has been well established in recent years. KLA’s 293x broadband plasma (BBP) optical patterned wafer inspection system uses a high intensity laser pumped plasma illumination source, which enables selectable wavelength bands, and is also optimized for a design-based care area methodology to inspect critical patterns with higher sensitivity and to reduce nuisance rates in noisy regions. In this study, by enabling a design-based care area, the CAB (care area border) size will be further reduced to 0.05 ~ 0.1µm to scan more of the critical area. In a WCMP layer, unique microscratch DOI were successfully detected in the SA (sense amplifier) region, and 8.6x higher contact missing defects were captured in the target region compared to the legacy care area methodology.
{"title":"Sensitivity Enhancement by Enabling Design-Based Inspection for DRAM","authors":"Y.M. Lu, J.W. Huang, K. Hsiao, Joe Chen, Alex T. Cheng","doi":"10.1109/ASMC.2019.8791745","DOIUrl":"https://doi.org/10.1109/ASMC.2019.8791745","url":null,"abstract":"With shrinking design rules, detecting tiny defects of interest (DOI) is becoming more challenging for wafer inspection tools. Using design-based care areas for inspection systems to characterize DOI has been well established in recent years. KLA’s 293x broadband plasma (BBP) optical patterned wafer inspection system uses a high intensity laser pumped plasma illumination source, which enables selectable wavelength bands, and is also optimized for a design-based care area methodology to inspect critical patterns with higher sensitivity and to reduce nuisance rates in noisy regions. In this study, by enabling a design-based care area, the CAB (care area border) size will be further reduced to 0.05 ~ 0.1µm to scan more of the critical area. In a WCMP layer, unique microscratch DOI were successfully detected in the SA (sense amplifier) region, and 8.6x higher contact missing defects were captured in the target region compared to the legacy care area methodology.","PeriodicalId":287541,"journal":{"name":"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134412573","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-06DOI: 10.1109/ASMC.2019.8791820
D. Vaughn, Felix P. Anderson, R. Meunier, T. Doan, A. Stamper
GLOBALFOUNDRIES has ramped its 180nm generation RFSOI foundry technology into high volume production at multiple 200mm and 300mm fabricators. This RFSOI technology was optimized primarily for sub-6GHz RF switches, tuners, and low noise amplifiers used in cell phone front-end-modules. The thin SOI wafer top silicon layer presents challenges in contact etching and this paper summarizes the optimization of contact etching to significantly reduce the final contact dielectric thickness consumption and improve copper M1 wire to FET gate polysilicon (M1-Poly) shorting yield.
{"title":"Methods for RFSOI Damascene Tungsten Contact Etching","authors":"D. Vaughn, Felix P. Anderson, R. Meunier, T. Doan, A. Stamper","doi":"10.1109/ASMC.2019.8791820","DOIUrl":"https://doi.org/10.1109/ASMC.2019.8791820","url":null,"abstract":"GLOBALFOUNDRIES has ramped its 180nm generation RFSOI foundry technology into high volume production at multiple 200mm and 300mm fabricators. This RFSOI technology was optimized primarily for sub-6GHz RF switches, tuners, and low noise amplifiers used in cell phone front-end-modules. The thin SOI wafer top silicon layer presents challenges in contact etching and this paper summarizes the optimization of contact etching to significantly reduce the final contact dielectric thickness consumption and improve copper M1 wire to FET gate polysilicon (M1-Poly) shorting yield.","PeriodicalId":287541,"journal":{"name":"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116838033","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-06DOI: 10.1109/ASMC.2019.8791761
A. Rahman, Aunik K. Rahman
Modern integrated circuit (IC) packaging faces challenges for higher speed in a smaller dimension achieved due to the 10 nm or smaller process node. While ICs are being packaged in 3D format, it is often not possible to measure features and/or defects in a non-destructive route. This paper reports a technique for nanometrology using bigger wavelengths such as those within the terahertz range. Practical measurements of dot pattern and other patterns on a 3D chip under the surface have been carried out. Two graphene have been imaged for quantifying the number of layers in the exfoliate also the thickness of each graphene sheet in the exfoliate. The results check out well compared to the standard techniques such as the SEM. In addition, a criterion for graphene’s quality assessment in terms of direct measurement of number of sheets in an exfoliate has been proposed. Thus, the nanometrology reported here, is a versatile tool for nanoscale measurements.
{"title":"Sub-surface nanometrology of semiconductor wafers and graphene quality assessment via terahertz route","authors":"A. Rahman, Aunik K. Rahman","doi":"10.1109/ASMC.2019.8791761","DOIUrl":"https://doi.org/10.1109/ASMC.2019.8791761","url":null,"abstract":"Modern integrated circuit (IC) packaging faces challenges for higher speed in a smaller dimension achieved due to the 10 nm or smaller process node. While ICs are being packaged in 3D format, it is often not possible to measure features and/or defects in a non-destructive route. This paper reports a technique for nanometrology using bigger wavelengths such as those within the terahertz range. Practical measurements of dot pattern and other patterns on a 3D chip under the surface have been carried out. Two graphene have been imaged for quantifying the number of layers in the exfoliate also the thickness of each graphene sheet in the exfoliate. The results check out well compared to the standard techniques such as the SEM. In addition, a criterion for graphene’s quality assessment in terms of direct measurement of number of sheets in an exfoliate has been proposed. Thus, the nanometrology reported here, is a versatile tool for nanoscale measurements.","PeriodicalId":287541,"journal":{"name":"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122018434","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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