A gate matrix deformation and three-dimensional maze routing for dense MOS module generation

Abstract

A two-stage method is proposed for generating dense MOS modules. The first stage is generation of dense placements of FETs (field-effect transistors) from the gate-matrix layouts, using a gate matrix deformation method. The deformation of gate-matrix layouts is guided by the design rules, using FETs with meander channel structures if needed. The second stage is routing of metal wires to connect FETs in modules. The authors have developed a three-dimensional maze router by extending the method to cope with arbitrary multilayer connections with user-defined costs for the connections in each layer. The costs can be used to assign desired priorities for each metal layer in the routing. This method results in about 65% reduction in chip area compared with the gate matrix method for typical examples using three- or four-layer connections