A custom intelligent multiplexer/driver (IMD) IC was designed for use with an implantable three-channel ultrasonic pulsed Doppler blood flowmeter. It also facilitated the development of a system architecture for the three-channel flowmeter by adding only 0.8 mW to the 30 mW of power consumption in the implanted portion of the single-channel flowmeter. By sending RF command signals to the implanted electronics, the flowmeter can operate in either the single- or multichannel mode. A unique transducer multiplexing circuit was incorporated on the IMD to obtain a round-trip channel isolation of 38 dB while operating on a 2.7 V battery. This channel isolation is an order of magnitude superior to that obtained by an earlier approach. A power transistor was fabricated (on the IMD) with standard MOS processes to achieve an on-resistance of 3 Ω (at a gate-source voltage of 2.7 V) and rise and fall times of 10 ns for 6-MHz transducer excitation
{"title":"An intelligent multiplexer/driver integrated circuit for an implantable multichannel blood flowmeter","authors":"K.-W.W. Yeung, J. Meindl","doi":"10.1109/CICC.1989.56734","DOIUrl":"https://doi.org/10.1109/CICC.1989.56734","url":null,"abstract":"A custom intelligent multiplexer/driver (IMD) IC was designed for use with an implantable three-channel ultrasonic pulsed Doppler blood flowmeter. It also facilitated the development of a system architecture for the three-channel flowmeter by adding only 0.8 mW to the 30 mW of power consumption in the implanted portion of the single-channel flowmeter. By sending RF command signals to the implanted electronics, the flowmeter can operate in either the single- or multichannel mode. A unique transducer multiplexing circuit was incorporated on the IMD to obtain a round-trip channel isolation of 38 dB while operating on a 2.7 V battery. This channel isolation is an order of magnitude superior to that obtained by an earlier approach. A power transistor was fabricated (on the IMD) with standard MOS processes to achieve an on-resistance of 3 Ω (at a gate-source voltage of 2.7 V) and rise and fall times of 10 ns for 6-MHz transducer excitation","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"232 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115686602","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Momodomi, Y. Iwata, Tomoharu Tanaka, Y. Itoh, R. Shirota, F. Masuoka
A 5 V-only 4 Mb NAND EEPROM (electrically erasable programmable read-only memory) has been successfully developed. The EEPROM has on-chip high-voltage generators, so the system needs only a 5 V power supply. The block-page erase/program mode realizes high-speed programming. On-chip test circuits provide high reliability. The NAND EEPROM has many applications for compact microcomputer systems, which need large storage systems with low power consumption
{"title":"A high density NAND EEPROM with block-page programming for microcomputer applications","authors":"M. Momodomi, Y. Iwata, Tomoharu Tanaka, Y. Itoh, R. Shirota, F. Masuoka","doi":"10.1109/CICC.1989.56726","DOIUrl":"https://doi.org/10.1109/CICC.1989.56726","url":null,"abstract":"A 5 V-only 4 Mb NAND EEPROM (electrically erasable programmable read-only memory) has been successfully developed. The EEPROM has on-chip high-voltage generators, so the system needs only a 5 V power supply. The block-page erase/program mode realizes high-speed programming. On-chip test circuits provide high reliability. The NAND EEPROM has many applications for compact microcomputer systems, which need large storage systems with low power consumption","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121051454","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
W. Krenik, D. Gonzalez, E. G. Dierschke, L.J. Izzi, B. Carter, J. White, R. Miller
An optical metering system, including a custom photosensor and a 12-bit dual-slope analog-to-digital converter, has been developed. System requirements are discussed, and a design based on full integration of all active and passive circuit components is adopted. The design of system components and the performance levels achieved are covered in detail
{"title":"A precision optical metering system for medical instrumentation","authors":"W. Krenik, D. Gonzalez, E. G. Dierschke, L.J. Izzi, B. Carter, J. White, R. Miller","doi":"10.1109/CICC.1989.56707","DOIUrl":"https://doi.org/10.1109/CICC.1989.56707","url":null,"abstract":"An optical metering system, including a custom photosensor and a 12-bit dual-slope analog-to-digital converter, has been developed. System requirements are discussed, and a design based on full integration of all active and passive circuit components is adopted. The design of system components and the performance levels achieved are covered in detail","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127322772","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
R. Leung, K. Le, C. Sung, Y. Chu, G. Conner, R. Lane, J. de Jong
A BiCMOS PAL-type device is described. It has a propagation delay of 7.5 ns and consumes 350 mW of power. The circuit has eight inputs, four bidirectional input/outputs and four registered outputs (known as 16R4 in databooks). The technology is a twin-well, merged bipolar and CMOS (BiCMOS) process. The minimum feature size is 1.2 μm
{"title":"A 7.5 ns 350 mW BiCMOS PAL-type device","authors":"R. Leung, K. Le, C. Sung, Y. Chu, G. Conner, R. Lane, J. de Jong","doi":"10.1109/CICC.1989.56695","DOIUrl":"https://doi.org/10.1109/CICC.1989.56695","url":null,"abstract":"A BiCMOS PAL-type device is described. It has a propagation delay of 7.5 ns and consumes 350 mW of power. The circuit has eight inputs, four bidirectional input/outputs and four registered outputs (known as 16R4 in databooks). The technology is a twin-well, merged bipolar and CMOS (BiCMOS) process. The minimum feature size is 1.2 μm","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115998618","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Ligthart, A. Bechtolsheim, G. De Micheli, A. El Gamal
The design of a digital audio input output (DAIO) chip that interfaces a standard 16/32-bit microprocessor bus with audio devices based on the AES protocol is described. This novel design provides general-purpose microprocessor systems with the ability to communicate with compact-disk and digital-audio-tape players. The chip is designed, using high-level and logic synthesis tools, from a function description in a hardware description language
{"title":"Design of digital audio input output chip","authors":"M. Ligthart, A. Bechtolsheim, G. De Micheli, A. El Gamal","doi":"10.1109/CICC.1989.56758","DOIUrl":"https://doi.org/10.1109/CICC.1989.56758","url":null,"abstract":"The design of a digital audio input output (DAIO) chip that interfaces a standard 16/32-bit microprocessor bus with audio devices based on the AES protocol is described. This novel design provides general-purpose microprocessor systems with the ability to communicate with compact-disk and digital-audio-tape players. The chip is designed, using high-level and logic synthesis tools, from a function description in a hardware description language","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114182053","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The authors present a timing simulation environment that attempts to reduce the number of test patterns and features a novel multilevel timing simulator. In the proposed environment, the information contained in the logic description is used to recognize groups of test patterns that result in identical output transitions and therefore may be redundant. This information is also utilized to identify dormant subcircuits during the simulation. In addition, the authors describe a macromodeling methodology that provides multiple levels of modeling and further enhances the efficiency of the timing simulator
{"title":"A new multi-level timing simulation environment for timing verification","authors":"J. Benkoski, M. P. Chew, A. Strojwas","doi":"10.1109/CICC.1989.56746","DOIUrl":"https://doi.org/10.1109/CICC.1989.56746","url":null,"abstract":"The authors present a timing simulation environment that attempts to reduce the number of test patterns and features a novel multilevel timing simulator. In the proposed environment, the information contained in the logic description is used to recognize groups of test patterns that result in identical output transitions and therefore may be redundant. This information is also utilized to identify dormant subcircuits during the simulation. In addition, the authors describe a macromodeling methodology that provides multiple levels of modeling and further enhances the efficiency of the timing simulator","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129541720","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A three-transistor model is presented for simulating threshold voltage reduction due to the charge-sharing effect and damage induced degradation in submicrometer MOSFETs. The channel behavior is treated with three MOSFETs in series. These MOSFETs have different threshold voltages and mobilities due to charge sharing and surface damage. An analytic solution is derived, and the results agree with MINIMOS2 and experimental data. This model is simpler and more computationally efficient for circuit simulation than the usual 2-D numerical modeling approaches
{"title":"A three-transistor model for submicron MOSFET","authors":"S. Wong, H. Lin","doi":"10.1109/CICC.1989.56724","DOIUrl":"https://doi.org/10.1109/CICC.1989.56724","url":null,"abstract":"A three-transistor model is presented for simulating threshold voltage reduction due to the charge-sharing effect and damage induced degradation in submicrometer MOSFETs. The channel behavior is treated with three MOSFETs in series. These MOSFETs have different threshold voltages and mobilities due to charge sharing and surface damage. An analytic solution is derived, and the results agree with MINIMOS2 and experimental data. This model is simpler and more computationally efficient for circuit simulation than the usual 2-D numerical modeling approaches","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128644996","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Shih-Wei Sun, M. Swenson, J. Yeargain, C. Lee, C. Swift, J. Pfiester, W. Bibeau, W. Atwell
The process architecture and device characteristics of a submicrometer CMOS n+/p+ poly gate, Ti-salicide, double-metal technology are described. Tradeoffs among circuit shrinkability, device gain, and hot-carrier-injection susceptibility are discussed. This technology has been successfully implemented in a 0.8-μm unified-design-rule high-performance high-end MPU product
{"title":"A dual-poly (n+/p+) gate, Ti-salicide, double-metal technology for submicron CMOS ASIC and logic applications","authors":"Shih-Wei Sun, M. Swenson, J. Yeargain, C. Lee, C. Swift, J. Pfiester, W. Bibeau, W. Atwell","doi":"10.1109/CICC.1989.56786","DOIUrl":"https://doi.org/10.1109/CICC.1989.56786","url":null,"abstract":"The process architecture and device characteristics of a submicrometer CMOS n+/p+ poly gate, Ti-salicide, double-metal technology are described. Tradeoffs among circuit shrinkability, device gain, and hot-carrier-injection susceptibility are discussed. This technology has been successfully implemented in a 0.8-μm unified-design-rule high-performance high-end MPU product","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129282818","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A novel configuration for two-step analog-to-digital (A/D) flash conversion is described. The coarse and fine conversions are performed with a four-bit multiplexed flash converter, so only 15 comparators are necessary for an eight-bit converter. The D/A conversion and the subtraction required for the circuit operation are performed using the charge redistribution technique. A test chip, integrated with a 3-μm CMOS technology (area=3 mm2), has demonstrated the effectiveness of the proposed configuration
{"title":"An 8-bit two-step flash A/D converter for video applications","authors":"A. Cremonesi, F. Maloberti, G. Torelli, C. Vacchi","doi":"10.1109/CICC.1989.56700","DOIUrl":"https://doi.org/10.1109/CICC.1989.56700","url":null,"abstract":"A novel configuration for two-step analog-to-digital (A/D) flash conversion is described. The coarse and fine conversions are performed with a four-bit multiplexed flash converter, so only 15 comparators are necessary for an eight-bit converter. The D/A conversion and the subtraction required for the circuit operation are performed using the charge redistribution technique. A test chip, integrated with a 3-μm CMOS technology (area=3 mm2), has demonstrated the effectiveness of the proposed configuration","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130508553","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
C. Ng, S. Ashtaputre, E. Chambers, Kieu-Huong Do, S.-T. Hui, R. Mody, D. Wong
The authors present an automatic layout system for designing large sea-of-gates gate arrays. This tool combines a floorplanning tool with an automatic placement and routing tool. It is designed to handle 250 K-gate arrays with special functional blocks such as RAM and ROM. It provides features for current processing, timing-driven layout, special clock distribution, and power distribution. The tool is currently being tested for designing the industry's most complex sea-of-gates gate arrays
{"title":"A hierarchical floor-planning, placement, and routing tool for sea-of-gates designs","authors":"C. Ng, S. Ashtaputre, E. Chambers, Kieu-Huong Do, S.-T. Hui, R. Mody, D. Wong","doi":"10.1109/CICC.1989.56680","DOIUrl":"https://doi.org/10.1109/CICC.1989.56680","url":null,"abstract":"The authors present an automatic layout system for designing large sea-of-gates gate arrays. This tool combines a floorplanning tool with an automatic placement and routing tool. It is designed to handle 250 K-gate arrays with special functional blocks such as RAM and ROM. It provides features for current processing, timing-driven layout, special clock distribution, and power distribution. The tool is currently being tested for designing the industry's most complex sea-of-gates gate arrays","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129135454","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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