A low-power processor for portable navigation devices: 456 mW at 400 MHz and 24 mW in software standby mode

Khoa Dac Tran, P. Van Nguyen, Hoa Tan Lu, Cuong Phuc Phan, Quang Phan, H. Kudo, H. Masuda, S. Negishi, M. Yamamoto, K. Hirose, Y. Okamoto
{"title":"A low-power processor for portable navigation devices: 456 mW at 400 MHz and 24 mW in software standby mode","authors":"Khoa Dac Tran, P. Van Nguyen, Hoa Tan Lu, Cuong Phuc Phan, Quang Phan, H. Kudo, H. Masuda, S. Negishi, M. Yamamoto, K. Hirose, Y. Okamoto","doi":"10.1109/ASSCC.2008.4708762","DOIUrl":null,"url":null,"abstract":"We have developed a processor (SH-MobileR2) optimized for both low power and high performance. SH-MobileR2 includes a 32-bit RISC type SuperH CPU with 720 MIPS performance at 400 MHz operating frequency, and a Floating Point unit with 2.8 GFLOPS performance. The CPU also has a 256-KByte secondary unified cache on top of the 64-KByte primary split cache. Compared to the previous SH-MobileR processor, SH-MobileR2 introduces four peripheral modules: a DDR-SDRAM controller, an Interconnect Buffers with 128-Kbyte embedded Media RAM, an improved Video Processing unit (VPU5F), and an enhanced 2-D Graphics accelerator for higher performance in map rendering and graphic applications. Low-power consumption is achieved by optimizing blends of a 90 nm CMOS triple Vth cells, and applying four power-down modes. The low-power consumption and the high performance of SH-MobileR2 processor is the most suitable for portable navigation devices.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":"41 11","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 IEEE Asian Solid-State Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASSCC.2008.4708762","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
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Abstract

We have developed a processor (SH-MobileR2) optimized for both low power and high performance. SH-MobileR2 includes a 32-bit RISC type SuperH CPU with 720 MIPS performance at 400 MHz operating frequency, and a Floating Point unit with 2.8 GFLOPS performance. The CPU also has a 256-KByte secondary unified cache on top of the 64-KByte primary split cache. Compared to the previous SH-MobileR processor, SH-MobileR2 introduces four peripheral modules: a DDR-SDRAM controller, an Interconnect Buffers with 128-Kbyte embedded Media RAM, an improved Video Processing unit (VPU5F), and an enhanced 2-D Graphics accelerator for higher performance in map rendering and graphic applications. Low-power consumption is achieved by optimizing blends of a 90 nm CMOS triple Vth cells, and applying four power-down modes. The low-power consumption and the high performance of SH-MobileR2 processor is the most suitable for portable navigation devices.
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用于便携式导航设备的低功耗处理器:400兆赫时为456兆瓦,软件待机模式下为24兆瓦
我们开发了一款处理器(SH-MobileR2),针对低功耗和高性能进行了优化。SH-MobileR2包括一个32位RISC型SuperH CPU,在400 MHz工作频率下具有720 MIPS的性能,以及一个2.8 GFLOPS性能的浮点单元。在64-KByte的主分割缓存之上,CPU还有一个256-KByte的辅助统一缓存。与之前的SH-MobileR处理器相比,SH-MobileR2引入了四个外围模块:一个DDR-SDRAM控制器,一个带有128 kbyte嵌入式媒体RAM的互连缓冲区,一个改进的视频处理单元(VPU5F),以及一个增强的二维图形加速器,以提高地图渲染和图形应用的性能。低功耗是通过优化90 nm CMOS三重Vth电池的混合,并采用四种断电模式来实现的。SH-MobileR2处理器的低功耗和高性能是最适合便携式导航设备的。
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