Khoa Dac Tran, P. Van Nguyen, Hoa Tan Lu, Cuong Phuc Phan, Quang Phan, H. Kudo, H. Masuda, S. Negishi, M. Yamamoto, K. Hirose, Y. Okamoto
{"title":"A low-power processor for portable navigation devices: 456 mW at 400 MHz and 24 mW in software standby mode","authors":"Khoa Dac Tran, P. Van Nguyen, Hoa Tan Lu, Cuong Phuc Phan, Quang Phan, H. Kudo, H. Masuda, S. Negishi, M. Yamamoto, K. Hirose, Y. Okamoto","doi":"10.1109/ASSCC.2008.4708762","DOIUrl":null,"url":null,"abstract":"We have developed a processor (SH-MobileR2) optimized for both low power and high performance. SH-MobileR2 includes a 32-bit RISC type SuperH CPU with 720 MIPS performance at 400 MHz operating frequency, and a Floating Point unit with 2.8 GFLOPS performance. The CPU also has a 256-KByte secondary unified cache on top of the 64-KByte primary split cache. Compared to the previous SH-MobileR processor, SH-MobileR2 introduces four peripheral modules: a DDR-SDRAM controller, an Interconnect Buffers with 128-Kbyte embedded Media RAM, an improved Video Processing unit (VPU5F), and an enhanced 2-D Graphics accelerator for higher performance in map rendering and graphic applications. Low-power consumption is achieved by optimizing blends of a 90 nm CMOS triple Vth cells, and applying four power-down modes. The low-power consumption and the high performance of SH-MobileR2 processor is the most suitable for portable navigation devices.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":"41 11","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 IEEE Asian Solid-State Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASSCC.2008.4708762","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
We have developed a processor (SH-MobileR2) optimized for both low power and high performance. SH-MobileR2 includes a 32-bit RISC type SuperH CPU with 720 MIPS performance at 400 MHz operating frequency, and a Floating Point unit with 2.8 GFLOPS performance. The CPU also has a 256-KByte secondary unified cache on top of the 64-KByte primary split cache. Compared to the previous SH-MobileR processor, SH-MobileR2 introduces four peripheral modules: a DDR-SDRAM controller, an Interconnect Buffers with 128-Kbyte embedded Media RAM, an improved Video Processing unit (VPU5F), and an enhanced 2-D Graphics accelerator for higher performance in map rendering and graphic applications. Low-power consumption is achieved by optimizing blends of a 90 nm CMOS triple Vth cells, and applying four power-down modes. The low-power consumption and the high performance of SH-MobileR2 processor is the most suitable for portable navigation devices.