Pub Date : 2008-12-12DOI: 10.1109/ASSCC.2008.4708728
K. Gotoh, H. Ando, A. Iwata
This paper describes a low-voltage design for a pipelined A/D converter that can operate in a 2.0-Vpp full-swing input range at a 1.0-V supply. To enlarge the input range of an ADC and maintain the output range of its op-amps, we propose a new front-end 2b-MDAC with S/H that can reduce the output range of all MDACs by 50% compared with the ADCpsilas input. We designed a 10-b pipelined ADC with the proposed 2b-MDAC. The fabricated ADC using a 90-nm CMOS process is able to operate in 2.0-Vpp full-swing input at a 1.0-V supply in spite of it using conventional op-amps, and has SNDR/SFDR of 57.5 dB/69.0 dB at 30 MS/s with only 3.4 mW.
{"title":"A 10-b 30-MS/s 3.4-mW pipelined ADC with 2.0-Vpp full-swing input at a 1.0-V supply","authors":"K. Gotoh, H. Ando, A. Iwata","doi":"10.1109/ASSCC.2008.4708728","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708728","url":null,"abstract":"This paper describes a low-voltage design for a pipelined A/D converter that can operate in a 2.0-Vpp full-swing input range at a 1.0-V supply. To enlarge the input range of an ADC and maintain the output range of its op-amps, we propose a new front-end 2b-MDAC with S/H that can reduce the output range of all MDACs by 50% compared with the ADCpsilas input. We designed a 10-b pipelined ADC with the proposed 2b-MDAC. The fabricated ADC using a 90-nm CMOS process is able to operate in 2.0-Vpp full-swing input at a 1.0-V supply in spite of it using conventional op-amps, and has SNDR/SFDR of 57.5 dB/69.0 dB at 30 MS/s with only 3.4 mW.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115265976","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-12DOI: 10.1109/ASSCC.2008.4708718
G. Gerosa, S. Curtis, M. D'Addeo, Bo Jiang, B. Kuttanna, F. Merchant, Binta Patel, M. H. Taufique, H. Samarchi
This paper describes a low power Intelreg Architecture (IA) processor specifically designed for mobile internet devices (MID). The design consists of an in-order pipeline capable of issuing 2 instructions per cycle supporting 2 threads, 32 KB instruction and 24 KB data L1 caches, independent integer and floating point execution units, a 512 KB L2 cache and a 533 MT/s dual-mode (GTL and CMOS) front-side-bus (FSB). The design contains 47 million transistors in a die size under 25 mm2 manufactured in a 9-metal 45 nm CMOS process. Thermal design power (TDP) consumption is measured at 2 W, 1.0 V, 90degC using a synthetic power-virus test at a frequency of 1.86 GHz.
{"title":"A sub 2W low power IA Processor for Mobile Internet Devices in 45nm Hi-K metal gate CMOS","authors":"G. Gerosa, S. Curtis, M. D'Addeo, Bo Jiang, B. Kuttanna, F. Merchant, Binta Patel, M. H. Taufique, H. Samarchi","doi":"10.1109/ASSCC.2008.4708718","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708718","url":null,"abstract":"This paper describes a low power Intelreg Architecture (IA) processor specifically designed for mobile internet devices (MID). The design consists of an in-order pipeline capable of issuing 2 instructions per cycle supporting 2 threads, 32 KB instruction and 24 KB data L1 caches, independent integer and floating point execution units, a 512 KB L2 cache and a 533 MT/s dual-mode (GTL and CMOS) front-side-bus (FSB). The design contains 47 million transistors in a die size under 25 mm2 manufactured in a 9-metal 45 nm CMOS process. Thermal design power (TDP) consumption is measured at 2 W, 1.0 V, 90degC using a synthetic power-virus test at a frequency of 1.86 GHz.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123698088","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-12DOI: 10.1109/ASSCC.2008.4708778
N. Sakimura, R. Nebashi, H. Honjo, S. Saito, Y. Kato, T. Sugibayashi
A 500-MHz MRAM macro is developed using a 0.15-mum CMOS process and a newly developed MRAM process. The macro is designed using a 20.17-mum2 5-transistor 2-magnetic tunnel junction (5T2MTJ) cell that has individual ports for writing and reading. An access time of less than 2 ns was obtained by employing a hierarchically-divided read bit line (RBL) and a high pre-charge sensing scheme. The operation speed is the highest among MRAMs that have been reported. This MRAM macro can coexist with the more area-effective 2TIMTJ-cell-based MRAM macro in SoCs.
采用0.15 μ m CMOS工艺和新开发的MRAM工艺开发了500 mhz MRAM宏。该宏设计使用20.17-mum2 5晶体管2磁隧道结(5T2MTJ)单元，具有用于写入和读取的单独端口。采用分层划分读位线(RBL)和高预电荷传感方案，获得了小于2 ns的访问时间。在已报道的mram中，其运行速度是最高的。在soc中，这个MRAM宏可以与更有效的基于2timtj细胞的MRAM宏共存。
{"title":"A 500-MHz MRAM macro for high-performance SoCs","authors":"N. Sakimura, R. Nebashi, H. Honjo, S. Saito, Y. Kato, T. Sugibayashi","doi":"10.1109/ASSCC.2008.4708778","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708778","url":null,"abstract":"A 500-MHz MRAM macro is developed using a 0.15-mum CMOS process and a newly developed MRAM process. The macro is designed using a 20.17-mum2 5-transistor 2-magnetic tunnel junction (5T2MTJ) cell that has individual ports for writing and reading. An access time of less than 2 ns was obtained by employing a hierarchically-divided read bit line (RBL) and a high pre-charge sensing scheme. The operation speed is the highest among MRAMs that have been reported. This MRAM macro can coexist with the more area-effective 2TIMTJ-cell-based MRAM macro in SoCs.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125400581","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-12DOI: 10.1109/ASSCC.2008.4708747
W. Chaivipas, K. Okada, A. Matsuzawa
A 80 GHz voltage controlled oscillator is presented. It is shown that impedance transformation enables the transformation of a varactor capacitance into negative varactor partially canceling the capacitance of the differential pair. This enables the transmission line resonator to be longer and have a higher impedance. Design criterion for achieving negative varactor is also presented, and design issues of millimeter wave voltage controlled oscillators are discussed. The voltage controlled oscillator is fabricated in 90 nm CMOS technology and achieves a phase noise of -109 dBc/Hz at 10 MHz offset with 13 mW power consumption from a 1.2 V power supply.
{"title":"A 80GHz voltage controlled oscillator utilizing a negative varactor in 90nm CMOS technology","authors":"W. Chaivipas, K. Okada, A. Matsuzawa","doi":"10.1109/ASSCC.2008.4708747","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708747","url":null,"abstract":"A 80 GHz voltage controlled oscillator is presented. It is shown that impedance transformation enables the transformation of a varactor capacitance into negative varactor partially canceling the capacitance of the differential pair. This enables the transmission line resonator to be longer and have a higher impedance. Design criterion for achieving negative varactor is also presented, and design issues of millimeter wave voltage controlled oscillators are discussed. The voltage controlled oscillator is fabricated in 90 nm CMOS technology and achieves a phase noise of -109 dBc/Hz at 10 MHz offset with 13 mW power consumption from a 1.2 V power supply.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115984268","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-12DOI: 10.1109/ASSCC.2008.4708752
T. Toifl, C. Menolfi, P. Buchmann, M. Kossel, T. Morf, M. Schmatz
We present a low dropout voltage regulator which uses a regulated replica in the loop in order to achieve small area, excellent power supply rejection over a wide frequency range, and high loop stability. The regulated replica provides accurate matching of the gm/gds ratio in the current source transistors for the replica and the load path. Power supply rejection of >22 dB was measured up to 1 GHz for a circuit operating at 0.8 V from a 1.0 V supply.
{"title":"A small-area voltage regulator with high-bandwidth supply-rejection using a regulated replica in 45nm CMOS SOI","authors":"T. Toifl, C. Menolfi, P. Buchmann, M. Kossel, T. Morf, M. Schmatz","doi":"10.1109/ASSCC.2008.4708752","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708752","url":null,"abstract":"We present a low dropout voltage regulator which uses a regulated replica in the loop in order to achieve small area, excellent power supply rejection over a wide frequency range, and high loop stability. The regulated replica provides accurate matching of the gm/gds ratio in the current source transistors for the replica and the load path. Power supply rejection of >22 dB was measured up to 1 GHz for a circuit operating at 0.8 V from a 1.0 V supply.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122290453","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-12DOI: 10.1109/ASSCC.2008.4708730
Moo-young Kim, Jinwoo Kim, Tagjong Lee, Chulwoo Kim
A 31 mW, 10-bit 100 MS/s pipelined ADC has been developed. The proposed ADC achieves low power consumption, high noise immunity, and small area by employing a new opamp sharing technique that switches the summing node in an MDAC and a current source with a PVT condition detector. The ADC shows a DNL of less than 0.48 LSB and an INL of less than 0.95 LSB. Also, a SNDR of 56.2 dB is measured with a 1 MHz input frequency. It has been implemented in a 0.18 um CMOS process and it occupies 1.6 x 0.8 mm2 of active area.
开发了一种31 mW, 10位100 MS/s的流水线ADC。所提出的ADC通过采用一种新的opamp共享技术，将MDAC中的求和节点和带PVT状态检测器的电流源切换，实现了低功耗、高抗噪性和小面积。ADC的DNL小于0.48 LSB, INL小于0.95 LSB。此外，在1 MHz输入频率下测量到56.2 dB的SNDR。它已在0.18 um CMOS工艺中实现，占用1.6 x 0.8 mm2的有源面积。
{"title":"10-bit 100MS/s CMOS pipelined A/D converter with 0.59pJ/conversion-step","authors":"Moo-young Kim, Jinwoo Kim, Tagjong Lee, Chulwoo Kim","doi":"10.1109/ASSCC.2008.4708730","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708730","url":null,"abstract":"A 31 mW, 10-bit 100 MS/s pipelined ADC has been developed. The proposed ADC achieves low power consumption, high noise immunity, and small area by employing a new opamp sharing technique that switches the summing node in an MDAC and a current source with a PVT condition detector. The ADC shows a DNL of less than 0.48 LSB and an INL of less than 0.95 LSB. Also, a SNDR of 56.2 dB is measured with a 1 MHz input frequency. It has been implemented in a 0.18 um CMOS process and it occupies 1.6 x 0.8 mm2 of active area.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124636018","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-12DOI: 10.1109/ASSCC.2008.4708825
Chin-Fu Li, Shih-chieh Chou, Po-Chiun Huang
This paper presents a noise suppression technique that is based on the feedback topology for wideband low-noise amplifiers. By nulling the signal in the noise feedback loop, the noise suppression and the signal performance like gain, input matching and output linearity can be considered independently. The overhead on power dissipation is small since the extra loop has less linearity concern. To demonstrate its feasibility, a shunt-feedback type LNA with the proposed noise suppression loop is implemented in a 0.18 mum CMOS process. The signal bandwidth is 1.3 GHz. The voltage gain and noise figure are 14.1 dB and 4.8 dB respectively. The current consumption is 1.18 mA from a 1.3 V supply voltage.
提出了一种基于反馈拓扑的宽带低噪声放大器噪声抑制技术。通过对噪声反馈回路中的信号进行零值处理，可以独立考虑噪声抑制和增益、输入匹配、输出线性等信号性能。由于额外环路具有较少的线性关系，因此功耗开销很小。为了证明其可行性，在0.18 μ m CMOS工艺中实现了带有所提出噪声抑制回路的分流反馈型LNA。信号带宽为1.3 GHz。电压增益和噪声系数分别为14.1 dB和4.8 dB。电流消耗为1.18 mA，来自1.3 V电源电压。
{"title":"A noise-suppressed amplifier with a signal-nulled feedback for wideband applications","authors":"Chin-Fu Li, Shih-chieh Chou, Po-Chiun Huang","doi":"10.1109/ASSCC.2008.4708825","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708825","url":null,"abstract":"This paper presents a noise suppression technique that is based on the feedback topology for wideband low-noise amplifiers. By nulling the signal in the noise feedback loop, the noise suppression and the signal performance like gain, input matching and output linearity can be considered independently. The overhead on power dissipation is small since the extra loop has less linearity concern. To demonstrate its feasibility, a shunt-feedback type LNA with the proposed noise suppression loop is implemented in a 0.18 mum CMOS process. The signal bandwidth is 1.3 GHz. The voltage gain and noise figure are 14.1 dB and 4.8 dB respectively. The current consumption is 1.18 mA from a 1.3 V supply voltage.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126976212","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-12DOI: 10.1109/ASSCC.2008.4708741
Lingwei Zhang, Hanjun Jiang, Xuguang Sun, Chun Zhang, Zhihua Wang
A passive RF signal receiving and power switch ASIC is proposed, designed and verified for remote AC power switch. This IC receives 915 MHz RF signals containing power switching commands, and switches on/off the AC power relay of a household appliance accordingly. The proposed ASIC only uses energy recovered from the received RF signal, and it consumes almost zero stand-by current. The wireless identification technique is adopted to improve its anti-disturbance performance. The ASIC is designed in the 0.18 mum CMOS process, and it occupies a core area of 0.9 mm2. It can work with an RF input power as low as of 40 muW, and the data receiving rate is ~25 kbps. The measured standby current is less than 10 nA. The designed ASIC has been verified in a wireless switch demo system which can be used to switch a 220 V AC bulb remotely.
提出、设计并验证了一种用于远程交流电源开关的无源射频信号接收和电源开关专用集成电路。该IC接收包含电源开关命令的915mhz射频信号，并据此开关家用电器的交流电源继电器。所提出的ASIC仅使用从接收到的射频信号中恢复的能量，并且它消耗的待机电流几乎为零。采用无线识别技术，提高了系统的抗干扰性能。ASIC采用0.18 mm CMOS工艺设计，其核心面积为0.9 mm2。它可以在低至40muw的射频输入功率下工作，数据接收速率为~ 25kbps。待机电流测量值小于10na。所设计的ASIC已在一个无线开关演示系统中得到验证，该系统可用于远程开关220v交流灯泡。
{"title":"A passive RF receiving and power switch ASIC for remote power control with zero stand-by power","authors":"Lingwei Zhang, Hanjun Jiang, Xuguang Sun, Chun Zhang, Zhihua Wang","doi":"10.1109/ASSCC.2008.4708741","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708741","url":null,"abstract":"A passive RF signal receiving and power switch ASIC is proposed, designed and verified for remote AC power switch. This IC receives 915 MHz RF signals containing power switching commands, and switches on/off the AC power relay of a household appliance accordingly. The proposed ASIC only uses energy recovered from the received RF signal, and it consumes almost zero stand-by current. The wireless identification technique is adopted to improve its anti-disturbance performance. The ASIC is designed in the 0.18 mum CMOS process, and it occupies a core area of 0.9 mm2. It can work with an RF input power as low as of 40 muW, and the data receiving rate is ~25 kbps. The measured standby current is less than 10 nA. The designed ASIC has been verified in a wireless switch demo system which can be used to switch a 220 V AC bulb remotely.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128180012","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-12DOI: 10.1109/ASSCC.2008.4708758
Chen-Haur Chang, Chuan-Yiu Lee, Shao-Yi Chien
A ray-triangle intersection unit design for ray-tracing in embedded systems is fabricated by TSMC 0.13 mum technology. Bounding volume hierarchy data structure is employed to reduce the on-chip memory requirement. Multi-threading technique is used in the traversal unit to improve the hardware utilization and performance. Moreover, the cost of intersection unit is optimized with folding technique and reconfigurable datapath. Furthermore, the memory bandwidth is reduced with the proposed multi-bank cache architecture. It can provide the processing speed of 50 M-intersections/s with only 2.88 mm2 in hardware cost.
{"title":"A 2.88mm2 50M-intersections/s ray-triangle intersection unit for interactive ray tracing","authors":"Chen-Haur Chang, Chuan-Yiu Lee, Shao-Yi Chien","doi":"10.1109/ASSCC.2008.4708758","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708758","url":null,"abstract":"A ray-triangle intersection unit design for ray-tracing in embedded systems is fabricated by TSMC 0.13 mum technology. Bounding volume hierarchy data structure is employed to reduce the on-chip memory requirement. Multi-threading technique is used in the traversal unit to improve the hardware utilization and performance. Moreover, the cost of intersection unit is optimized with folding technique and reconfigurable datapath. Furthermore, the memory bandwidth is reduced with the proposed multi-bank cache architecture. It can provide the processing speed of 50 M-intersections/s with only 2.88 mm2 in hardware cost.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121753557","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-12DOI: 10.1109/ASSCC.2008.4708818
A. Sai, T. Yamaji, T. Itakura
Sampling clock jitter degrades the dynamic range of an analog-to-digital converter (ADC). This paper describes a low jitter clock generator for next-generation mobile wireless terminals. The clock generator employs a novel slew rate balancing (SRB) circuit in a single-ended ring oscillator based VCO to suppress the VCO phase noise due to up-converted 1/f noise. The proposed clock generator is fabricated in a 90-nm CMOS technology. The measured results show that the SRB circuit reduces the VCO phase noise by 3-5 dB at the offset frequencies where the up-converted 1/f noise dominates. The clock generator achieves 3.0 ps rms integrated jitter. Required chip area is 0.18 mm2 and the power consumption is 9 mW.
{"title":"A low-jitter clock generator based on ring oscillator with 1/f noise reduction technique for next-generation mobile wireless terminals","authors":"A. Sai, T. Yamaji, T. Itakura","doi":"10.1109/ASSCC.2008.4708818","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708818","url":null,"abstract":"Sampling clock jitter degrades the dynamic range of an analog-to-digital converter (ADC). This paper describes a low jitter clock generator for next-generation mobile wireless terminals. The clock generator employs a novel slew rate balancing (SRB) circuit in a single-ended ring oscillator based VCO to suppress the VCO phase noise due to up-converted 1/f noise. The proposed clock generator is fabricated in a 90-nm CMOS technology. The measured results show that the SRB circuit reduces the VCO phase noise by 3-5 dB at the offset frequencies where the up-converted 1/f noise dominates. The clock generator achieves 3.0 ps rms integrated jitter. Required chip area is 0.18 mm2 and the power consumption is 9 mW.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131455457","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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