Communication based FPGA synthesis for multi-output Boolean functions

Christoph Scholl, P. Molitor
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引用次数: 19

Abstract

One of the crucial problems multi level logic synthesis techniques for multi output Boolean functions f=(f/sub 1/,...,f/sub m/):{0,1}/sup n//spl rarr/{0,1}/sup m/ have to deal with is finding sublogic which can be shared by different outputs, i.e., finding Boolean functions /spl alpha/=(/spl alpha//sub 1/,...,/spl alpha//sub h/):{0,1}/sup p//spl rarr/{0,1}/sup h/ which can be used as common sublogic of good realizations of f/sub 1/,...,f/sub m/. We present an efficient ROBDD based implementation of this common decomposition functions problem (CDF). Formally, CDF is defined as follows: given m Boolean functions f/sub 1/,...,f/sub m/:{0,1}/sup n//spl rarr/{0,1}, and two natural numbers p and h, find h Boolean functions /spl alpha//sub 1/,..., /spl alpha//sub h/:{0, 1}/sup p//spl rarr/{0,1} such that /spl forall/1/spl les/k/spl les/m there is a decomposition of f/sub k/ of the form: f/sub k/(x/sub 1/,...x/sub n/)=g/sup (k)/(/spl alpha//sub 1/(x/sub 1/,...x/sub p/),...,/spl alpha//sub h/(x/sub 1/,...,x/sub p/),/spl alpha//sub h+1//sup (k)/(x/sub 1/,...,x/sub p/),...,/spl alpha/(r/sub k/)/sup (k)/(x/sub 1/,...x/sub p/),x/sub p+1/,...,x/sub n/) using a minimal number r/sub k/ of single output Boolean decomposition functions. Experimental results applying the method to FPGA synthesis are promising.
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基于通信的多输出布尔函数的FPGA合成
多输出布尔函数f=(f/下标1/,…,f/sub m/):{0,1}/sup n//spl rarr/{0,1}/sup m/必须处理的是找到可以由不同输出共享的子逻辑,即找到布尔函数/spl alpha/=(/spl alpha//sub 1/,…,/spl alpha//sub h/):{0,1}/sup p//spl rarr/{0,1}/sup h/可作为f/sub 1/,…的良好实现的公共子逻辑。f / m /。我们提出了一个有效的基于ROBDD的常见分解函数问题(CDF)实现。形式上,CDF定义如下:给定m个布尔函数f/sub 1/,…,f/sub m/:{0,1}/sup n//spl rarr/{0,1},和两个自然数p和h,找到h布尔函数/spl alpha//sub 1/,…, /spl alpha//sub h/:{0,1} /sup p//spl rarr/{0,1}使得/spl forall/1/spl les/k/spl les/m对f/sub k/进行分解,形式为:f/sub k/(x/sub 1/,…x / an /) = g /一口(k) / (/ splα/ /子1 / (x /订阅1 /…x /子/页),……,/spl alpha//sub h/(x/sub 1/,…, x /子p /) / splα/ /子h + 1 / /一口(k) / (x /订阅1 /…, x /子/页),…,/spl alpha/(r/下标k/)/sup (k)/(x/下标1/,…X / p/), X / p+1/,…,x/下标n/),使用最小值r/下标k/的单输出布尔分解函数。将该方法应用于FPGA合成的实验结果是令人满意的。
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