Pub Date : 1996-06-25DOI: 10.1109/ASPDAC.1995.486231
H. Miyashita
Pitchmatching algorithms are widely used in layout environments where no grid constraints are imposed. However, realistic layouts include multiple grid constraints which facilitate the applications of automatic routing. Hence, pitchmatching algorithms should be extended to those realistic layouts. The paper formulates a pitchmatching problem with multiple grid constraints. An algorithm for solving this problem is constructed by extending conventional pitchmatching algorithms. The computational complexity is also discussed in comparison with a conventional naive algorithm. Finally, examples and application results to realistic layouts are presented.
{"title":"Extending pitchmatching algorithms to layouts with multiple grid constraints","authors":"H. Miyashita","doi":"10.1109/ASPDAC.1995.486231","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486231","url":null,"abstract":"Pitchmatching algorithms are widely used in layout environments where no grid constraints are imposed. However, realistic layouts include multiple grid constraints which facilitate the applications of automatic routing. Hence, pitchmatching algorithms should be extended to those realistic layouts. The paper formulates a pitchmatching problem with multiple grid constraints. An algorithm for solving this problem is constructed by extending conventional pitchmatching algorithms. The computational complexity is also discussed in comparison with a conventional naive algorithm. Finally, examples and application results to realistic layouts are presented.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116943717","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-29DOI: 10.1109/ASPDAC.1995.486405
D. Brasen, J. P. Hiol, G. Saucier
The implementation of circuits with FPGAs commonly requires partitioning into several FPGA packages. A good FPGA package partitioning tool minimizes production cost by minimizing packages required without significantly increasing the circuit operational frequency. Prior work has shown that good results can be obtained by partitioning with cone structures. Cone structure partitioning is combined with random cluster creation for better FPGA package partitioning. Experimental results show that the final partitioning algorithm presented, produces better circuit partitions than the high quality Min-Cut tool of MCNC.
{"title":"Finding best cones from random clusters for FPGA package partitioning","authors":"D. Brasen, J. P. Hiol, G. Saucier","doi":"10.1109/ASPDAC.1995.486405","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486405","url":null,"abstract":"The implementation of circuits with FPGAs commonly requires partitioning into several FPGA packages. A good FPGA package partitioning tool minimizes production cost by minimizing packages required without significantly increasing the circuit operational frequency. Prior work has shown that good results can be obtained by partitioning with cone structures. Cone structure partitioning is combined with random cluster creation for better FPGA package partitioning. Experimental results show that the final partitioning algorithm presented, produces better circuit partitions than the high quality Min-Cut tool of MCNC.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"117 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116415834","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-29DOI: 10.1109/ASPDAC.1995.486412
M. Johann, R. da Luz Reis
This paper describes a Full Over-the-Cell routing model to perform circuit connections over the transistors by using "transparent cells". The methodology provides flexibility and the resulting layout style presents interesting performance/cost ratios if compared to those produced by Standard Cell and traditional Over-the-Cell routing models. A symbolic environment is shown, where it is possible to make the routing over real cell layouts, based on a restriction matrix. Some special routing techniques are mentioned and practical results are shown.
{"title":"A Full Over-the-Cell routing model","authors":"M. Johann, R. da Luz Reis","doi":"10.1109/ASPDAC.1995.486412","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486412","url":null,"abstract":"This paper describes a Full Over-the-Cell routing model to perform circuit connections over the transistors by using \"transparent cells\". The methodology provides flexibility and the resulting layout style presents interesting performance/cost ratios if compared to those produced by Standard Cell and traditional Over-the-Cell routing models. A symbolic environment is shown, where it is possible to make the routing over real cell layouts, based on a restriction matrix. Some special routing techniques are mentioned and practical results are shown.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116573369","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-29DOI: 10.1109/ASPDAC.1995.486406
R. Drechsler, B. Becker, A. Jahnke
We present methods for the construction of small ordered Kronecker functional decision diagrams (OKFDDs). OKFDDs are a generalization of ordered binary decision diagrams (OBDDs) and ordered functional decision diagrams (OFDDs) as well. Starting with an upper bound for the size of an OKFDD representing a tree like circuit, we develop different heuristics to find good variable orderings and decomposition types for OKFDDs representing two level and multi level circuits, respectively. Experimental results are presented to show the efficiency of our approaches.
{"title":"On variable ordering and decomposition type choice in OKFDDs","authors":"R. Drechsler, B. Becker, A. Jahnke","doi":"10.1109/ASPDAC.1995.486406","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486406","url":null,"abstract":"We present methods for the construction of small ordered Kronecker functional decision diagrams (OKFDDs). OKFDDs are a generalization of ordered binary decision diagrams (OBDDs) and ordered functional decision diagrams (OFDDs) as well. Starting with an upper bound for the size of an OKFDD representing a tree like circuit, we develop different heuristics to find good variable orderings and decomposition types for OKFDDs representing two level and multi level circuits, respectively. Experimental results are presented to show the efficiency of our approaches.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124548126","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-29DOI: 10.1109/ASPDAC.1995.486401
M. Bombana, R. B. Hughes, G. Musgrave
Specification languages with a sound and well established semantics are applied to the definition of hardware devices. Exploiting these formalisms, theorem provers are introduced in the design flow to guarantee the equivalence of the different abstraction levels involved in the process of behavioural synthesis. Design constraints, such as area and timing, are evaluated linking this design phase to the logic synthesis level. The benefits of applying this design methodology are highlighted through the analysis of the design of an application specific integrated circuit (ASIC) of medium complexity in the telecom domain.
{"title":"A mathematically sound approach to the correct design of hardware","authors":"M. Bombana, R. B. Hughes, G. Musgrave","doi":"10.1109/ASPDAC.1995.486401","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486401","url":null,"abstract":"Specification languages with a sound and well established semantics are applied to the definition of hardware devices. Exploiting these formalisms, theorem provers are introduced in the design flow to guarantee the equivalence of the different abstraction levels involved in the process of behavioural synthesis. Design constraints, such as area and timing, are evaluated linking this design phase to the logic synthesis level. The benefits of applying this design methodology are highlighted through the analysis of the design of an application specific integrated circuit (ASIC) of medium complexity in the telecom domain.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"167 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121310000","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-29DOI: 10.1109/ASPDAC.1995.486407
L. Torres, M. Robert, E. Bourennane, M. Paindavoine
We present the design of a real time image processing circuit based on an optimized Canny Deriche filter for ramp edge detection. This filter is implemented in a recursive form. A retiming method is used to achieve very high speed filtering. The edge calculation function has been implemented using a CMOS 1 /spl mu/m process (area 29 mm/sup 2/). This ASIC is able to process a pixel in less than 30 ns and image sizes from 64/spl times/64 to 1024/spl times/1024 pixels.
{"title":"Implementation of a recursive real time edge detector using retiming techniques","authors":"L. Torres, M. Robert, E. Bourennane, M. Paindavoine","doi":"10.1109/ASPDAC.1995.486407","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486407","url":null,"abstract":"We present the design of a real time image processing circuit based on an optimized Canny Deriche filter for ramp edge detection. This filter is implemented in a recursive form. A retiming method is used to achieve very high speed filtering. The edge calculation function has been implemented using a CMOS 1 /spl mu/m process (area 29 mm/sup 2/). This ASIC is able to process a pixel in less than 30 ns and image sizes from 64/spl times/64 to 1024/spl times/1024 pixels.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124160388","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-29DOI: 10.1109/ASPDAC.1995.486372
Zijian Zhou, Xiao-kang Song, F. Corella, E. Cerny, M. Langevin
Traditional OBDD-based methods of automated verification suffer from, the drawback that they require a binary representation of the circuit. Multiway Decision Graphs (MDGs) combine the advantages of OBDD techniques with those of abstract types. RTL designs can be compactly described by MDGs using abstract data values and uninterpreted function symbols. We have developed MDG-based techniques for combinational verification, reachability analysis, verification of behavioral equivalence, and verification of a microprocessor against its instruction set architecture. We report on the results of several verification experiments using our MDG package.
{"title":"Description and verification of RTL designs using multiway decision graphs","authors":"Zijian Zhou, Xiao-kang Song, F. Corella, E. Cerny, M. Langevin","doi":"10.1109/ASPDAC.1995.486372","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486372","url":null,"abstract":"Traditional OBDD-based methods of automated verification suffer from, the drawback that they require a binary representation of the circuit. Multiway Decision Graphs (MDGs) combine the advantages of OBDD techniques with those of abstract types. RTL designs can be compactly described by MDGs using abstract data values and uninterpreted function symbols. We have developed MDG-based techniques for combinational verification, reachability analysis, verification of behavioral equivalence, and verification of a microprocessor against its instruction set architecture. We report on the results of several verification experiments using our MDG package.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126475073","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-29DOI: 10.1109/ASPDAC.1995.486395
I. Ahmad, M. Dhodhi, K. Saleh
In this paper we present a variant of the simulated evolution technique for local microcode compaction. The simulated evolution is a general optimization method based on an analogy with the natural selection process in biological evolution. The proposed technique combines simulated evolution with list scheduling, in which simulated evolution is used to determine suitable priorities which lead to a good solution by applying list scheduling as a decoding heuristic. The proposed technique is an effective method that yields good results without problem-specific parameter tuning on test problems. We demonstrate the effectiveness of our technique by comparing it with the existing microcode compaction techniques for randomly generated data dependency graphs. The proposed scheme offers considerable improvement in the number of microinstructions compared with the existing techniques with comparable cpu time.
{"title":"An evolution-based technique for local microcode compaction","authors":"I. Ahmad, M. Dhodhi, K. Saleh","doi":"10.1109/ASPDAC.1995.486395","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486395","url":null,"abstract":"In this paper we present a variant of the simulated evolution technique for local microcode compaction. The simulated evolution is a general optimization method based on an analogy with the natural selection process in biological evolution. The proposed technique combines simulated evolution with list scheduling, in which simulated evolution is used to determine suitable priorities which lead to a good solution by applying list scheduling as a decoding heuristic. The proposed technique is an effective method that yields good results without problem-specific parameter tuning on test problems. We demonstrate the effectiveness of our technique by comparing it with the existing microcode compaction techniques for randomly generated data dependency graphs. The proposed scheme offers considerable improvement in the number of microinstructions compared with the existing techniques with comparable cpu time.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125598917","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-29DOI: 10.1109/ASPDAC.1995.486362
P. J. Windley
Recently there has been much research in verifying pipelined microprocessors. Even so, there has been little consensus on what form the correctness statement should take. Put another way, what should we be verifying about pipelined microprocessors? We believe that the correctness statement should show that the parallel machine represented by the pipeline behaves in the same manner as the sequential machine represented by the instruction set semantics. In this paper, we present such a model and examine four pipeline verifications to see how they compare.
{"title":"Verifying pipelined microprocessors","authors":"P. J. Windley","doi":"10.1109/ASPDAC.1995.486362","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486362","url":null,"abstract":"Recently there has been much research in verifying pipelined microprocessors. Even so, there has been little consensus on what form the correctness statement should take. Put another way, what should we be verifying about pipelined microprocessors? We believe that the correctness statement should show that the parallel machine represented by the pipeline behaves in the same manner as the sequential machine represented by the instruction set semantics. In this paper, we present such a model and examine four pipeline verifications to see how they compare.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130068659","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-29DOI: 10.1109/ASPDAC.1995.486393
R. Evans
We present a novel and extremely simple technique for performing concurrent error detection in arithmetic circuits such as those used in Digital Signal Processing (DSP). Our approach, called Algebraic Error Detection, employs the well known concept of time redundancy, but exploits the algebraic properties of the number representation used within the circuit to permit errors to be detected. Within certain constraints, our approach appears to be capable of detecting all errors caused by single stuck-at faults, both permanent and transient, as well as many multiple faults, and may also be applicable to existing DSP chips. We also describe two hardware systems developed to demonstrate the idea.
{"title":"Algebraic error detection: a new approach to concurrent error detection in arithmetic circuits","authors":"R. Evans","doi":"10.1109/ASPDAC.1995.486393","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486393","url":null,"abstract":"We present a novel and extremely simple technique for performing concurrent error detection in arithmetic circuits such as those used in Digital Signal Processing (DSP). Our approach, called Algebraic Error Detection, employs the well known concept of time redundancy, but exploits the algebraic properties of the number representation used within the circuit to permit errors to be detected. Within certain constraints, our approach appears to be capable of detecting all errors caused by single stuck-at faults, both permanent and transient, as well as many multiple faults, and may also be applicable to existing DSP chips. We also describe two hardware systems developed to demonstrate the idea.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134350773","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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