{"title":"Multiband RF-interconnect for CMP inter-core communications","authors":"M. Chang","doi":"10.1109/ICSICT.2008.4734915","DOIUrl":null,"url":null,"abstract":"In this paper, we propose a novel on-chip global interconnect that would meet stringent challenges of core-to-core communications in data rate (up to 100 Gbps /link), latency and re-configurability for future chip-microprocessors (CMP) with efficient area and energy overheads. We discuss the limitations of traditional RC-limited interconnects and possible benefits of multi-band RF-interconnect (RF-I) through on-chip differential transmission lines. The physical implementation of RF-I and its projected performance versus overhead as the function of CMOS technology scaling are addressed as well.","PeriodicalId":436457,"journal":{"name":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","volume":" 3","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICSICT.2008.4734915","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
In this paper, we propose a novel on-chip global interconnect that would meet stringent challenges of core-to-core communications in data rate (up to 100 Gbps /link), latency and re-configurability for future chip-microprocessors (CMP) with efficient area and energy overheads. We discuss the limitations of traditional RC-limited interconnects and possible benefits of multi-band RF-interconnect (RF-I) through on-chip differential transmission lines. The physical implementation of RF-I and its projected performance versus overhead as the function of CMOS technology scaling are addressed as well.