Pub Date : 2008-12-30DOI: 10.1109/ICSICT.2008.4734754
Y. Tseng, Jyi-Tsong Lin, Y. Eng, Shiang-Shi Kang, Hung-Jen Tseng, Ying-Chieh Tsai, B. Jheng, Po-Hsieh Lin
This paper proposes a new self-aligned process to form the silicon-on-insulator with block oxide. Based on the TCAD simulation, we have proved that the new process can get excellent short-channel effects immunity compared to the previous process [1]. Also, the new process can overcome the problem of the previous one, which can not be used on the thin BOX devices, so that the application of the block oxide can be applied extensively. In addition, we study how the height of the block oxide affects the devices performance in detail. Finally, we demonstrate a novel floating body cell using block oxide for 1T-DRAM application and its memory characteristics, large programming window and low leakage, are better than the conventional counterpart.
{"title":"A new process for self-aligned silicon-on-insulator with block oxide and its memory application for 1T-DRAM","authors":"Y. Tseng, Jyi-Tsong Lin, Y. Eng, Shiang-Shi Kang, Hung-Jen Tseng, Ying-Chieh Tsai, B. Jheng, Po-Hsieh Lin","doi":"10.1109/ICSICT.2008.4734754","DOIUrl":"https://doi.org/10.1109/ICSICT.2008.4734754","url":null,"abstract":"This paper proposes a new self-aligned process to form the silicon-on-insulator with block oxide. Based on the TCAD simulation, we have proved that the new process can get excellent short-channel effects immunity compared to the previous process [1]. Also, the new process can overcome the problem of the previous one, which can not be used on the thin BOX devices, so that the application of the block oxide can be applied extensively. In addition, we study how the height of the block oxide affects the devices performance in detail. Finally, we demonstrate a novel floating body cell using block oxide for 1T-DRAM application and its memory characteristics, large programming window and low leakage, are better than the conventional counterpart.","PeriodicalId":436457,"journal":{"name":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115162532","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-30DOI: 10.1109/ICSICT.2008.4734777
Y. Nara, N. Mise, M. Kadoshima, T. Morooka, S. Kamiyama, T. Matsuki, M. Sato, T. Ono, T. Aoyama, T. Eimori, Y. Ohji
Practical and manufacturable solutions for metal gate/dual high-k CMOS integration are presented. In order to overcome the difficulties of threshold voltage control of metal gate/high-k gate stack especially for gate-first integration, several material designs have been proposed so far. These include different metal gate materials and different high-k materials which are separately used in nMOS and pMOS transistors. These approaches sometimes bring about complicated CMOS integration scheme. In this paper, therefore, we will give simple metal gate/dual high-k CMOS fabrication processes with low threshold voltages which are suitable for scaled CMOS device manufacturing.
{"title":"Gate-first high-k/metal gate stack for advanced CMOS technology","authors":"Y. Nara, N. Mise, M. Kadoshima, T. Morooka, S. Kamiyama, T. Matsuki, M. Sato, T. Ono, T. Aoyama, T. Eimori, Y. Ohji","doi":"10.1109/ICSICT.2008.4734777","DOIUrl":"https://doi.org/10.1109/ICSICT.2008.4734777","url":null,"abstract":"Practical and manufacturable solutions for metal gate/dual high-k CMOS integration are presented. In order to overcome the difficulties of threshold voltage control of metal gate/high-k gate stack especially for gate-first integration, several material designs have been proposed so far. These include different metal gate materials and different high-k materials which are separately used in nMOS and pMOS transistors. These approaches sometimes bring about complicated CMOS integration scheme. In this paper, therefore, we will give simple metal gate/dual high-k CMOS fabrication processes with low threshold voltages which are suitable for scaled CMOS device manufacturing.","PeriodicalId":436457,"journal":{"name":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","volume":"110 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123089232","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-30DOI: 10.1109/ICSICT.2008.4734507
Qian Qinsong, Wu Hong, Li Haisong, Sun Weifeng
In this paper, the 2nd LEDMOS devices based on bulk silicon(BS) process for an advanced PDP data driver IC have been developed. Not only the on-state characteristics, but also the reliabilities of 2nd LEDMOS transistors such as hot carrier effect, Kirk effect issues are improved against the 1st LEDMOS. The devices can be realized by shrinking the cell size and partly changing the structure of the devices. And by applying the 2nd LEDMOS to the new PDP Driver IC, we have succeeded in reducing the die size of the IC to about 70% comparing with that of 1st one, but its number of output stages is increased by 1.33 times and the power dissipation of the new IC is reduced by more than 15% too.
{"title":"Bulk silicon CDMOS technology for an advanced PDP data drvier IC","authors":"Qian Qinsong, Wu Hong, Li Haisong, Sun Weifeng","doi":"10.1109/ICSICT.2008.4734507","DOIUrl":"https://doi.org/10.1109/ICSICT.2008.4734507","url":null,"abstract":"In this paper, the 2nd LEDMOS devices based on bulk silicon(BS) process for an advanced PDP data driver IC have been developed. Not only the on-state characteristics, but also the reliabilities of 2nd LEDMOS transistors such as hot carrier effect, Kirk effect issues are improved against the 1st LEDMOS. The devices can be realized by shrinking the cell size and partly changing the structure of the devices. And by applying the 2nd LEDMOS to the new PDP Driver IC, we have succeeded in reducing the die size of the IC to about 70% comparing with that of 1st one, but its number of output stages is increased by 1.33 times and the power dissipation of the new IC is reduced by more than 15% too.","PeriodicalId":436457,"journal":{"name":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116639681","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-30DOI: 10.1109/ICSICT.2008.4734482
Ran Liu
Although the strained-Si channel engineering seems to be rather compatible with the existing mainstream CMOS process, the use of strained Si on SOI virtual substrates introduces new process and integration issues that need to be addressed for successful manufacturability and reliability. Even for ideal strained Si on SOI substrates, the impacts of various CMOS process steps, e.g., patterning, oxidation, implantation and annealing, on strain relaxation, defect formation and Ge interdiffusion need to be well understood and controlled before feasible process integration can be achieved. In this work, we investigate the influences of pad oxidation, gate oxidation and dopant-activation annealling on strained Si on SOI heterostructures by using UV micro-Raman spectroscopy in combination with other characterization techniques, such as Auger electron spectroscopy (AES), atomic force microscopy (AFM), high resolution x-ray diffraction (HRXRD), secondary ion mass spectrometry (SIMS), transmission electron microscopy (TEM).
{"title":"Process characterization for strained Si on SOI CMOS devices","authors":"Ran Liu","doi":"10.1109/ICSICT.2008.4734482","DOIUrl":"https://doi.org/10.1109/ICSICT.2008.4734482","url":null,"abstract":"Although the strained-Si channel engineering seems to be rather compatible with the existing mainstream CMOS process, the use of strained Si on SOI virtual substrates introduces new process and integration issues that need to be addressed for successful manufacturability and reliability. Even for ideal strained Si on SOI substrates, the impacts of various CMOS process steps, e.g., patterning, oxidation, implantation and annealing, on strain relaxation, defect formation and Ge interdiffusion need to be well understood and controlled before feasible process integration can be achieved. In this work, we investigate the influences of pad oxidation, gate oxidation and dopant-activation annealling on strained Si on SOI heterostructures by using UV micro-Raman spectroscopy in combination with other characterization techniques, such as Auger electron spectroscopy (AES), atomic force microscopy (AFM), high resolution x-ray diffraction (HRXRD), secondary ion mass spectrometry (SIMS), transmission electron microscopy (TEM).","PeriodicalId":436457,"journal":{"name":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116779939","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-30DOI: 10.1109/ICSICT.2008.4734779
Kenji Shiraishi, Takashi Nakayama, Seiichi Miyazaki, A. Ohta, Y. Akasaka, Heiji Watanabe, Yasuo Nara, K. Yamada
We have found that effective work functions of high-work function gate metals (p-metals) become small and Fermi level pinning of gate metals occurs after high temperature treatment as the same in the case in p+poly-Si gates. On the contrary, intrinsic hybridization between metal and high-k wave function at the interface is crucial factor to determine effective work function of gate metals after low temperature treatment. As discussed above, metal/high-k interface properties are much different each other after high- and low-temperature treatment.
{"title":"Theoretical investigations on metal/high-k interfaces","authors":"Kenji Shiraishi, Takashi Nakayama, Seiichi Miyazaki, A. Ohta, Y. Akasaka, Heiji Watanabe, Yasuo Nara, K. Yamada","doi":"10.1109/ICSICT.2008.4734779","DOIUrl":"https://doi.org/10.1109/ICSICT.2008.4734779","url":null,"abstract":"We have found that effective work functions of high-work function gate metals (p-metals) become small and Fermi level pinning of gate metals occurs after high temperature treatment as the same in the case in p+poly-Si gates. On the contrary, intrinsic hybridization between metal and high-k wave function at the interface is crucial factor to determine effective work function of gate metals after low temperature treatment. As discussed above, metal/high-k interface properties are much different each other after high- and low-temperature treatment.","PeriodicalId":436457,"journal":{"name":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117185084","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-30DOI: 10.1109/ICSICT.2008.4735009
Xiaoxin Cui, Chungan Peng
The conventional matched filter structures are investigated in this paper. An acquisition circuit based on the polyphase form matched filter in Global Positioning System (GPS) receiver is provided. At the cost of less hardware resource, the significant advantage in the speed of synchronization is offered. For 32×128 polyphase form matched filter, the critical path delay approximately reduces 1/2, the sample frequency would be double.
{"title":"An acquisition circuit in Global Positioning System receivers","authors":"Xiaoxin Cui, Chungan Peng","doi":"10.1109/ICSICT.2008.4735009","DOIUrl":"https://doi.org/10.1109/ICSICT.2008.4735009","url":null,"abstract":"The conventional matched filter structures are investigated in this paper. An acquisition circuit based on the polyphase form matched filter in Global Positioning System (GPS) receiver is provided. At the cost of less hardware resource, the significant advantage in the speed of synchronization is offered. For 32×128 polyphase form matched filter, the critical path delay approximately reduces 1/2, the sample frequency would be double.","PeriodicalId":436457,"journal":{"name":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","volume":"92 24","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120818952","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-30DOI: 10.1109/ICSICT.2008.4734602
T. Ward, Jian Shen
The two hottest areas of research in condensed matter physics are complexity and nanoscale physics. Interestingly, these two areas have little overlap as most of the nanophysics research work is conducted using ¿simple¿ materials of metals or semiconductors instead of complex materials such as transition metal oxides. However, due to the strong electronic correlation, it is exactly the transition metal oxides that will most likely lead to observations of striking new phenomena under spatial confinement. We will use perovskite manganites as model systems to demonstrate how spatial confinement can dramatically affect their transport and magnetic properties. The emerging magnetic and transport behavior is likely associated with the electronic phase separation under confined geometry in the manganites. Some of the new properties such as ultrasharp jumps of magnetoresistance and reentrant metal-insulator transition may have significant impact on fabricating oxides-based novel devices.
{"title":"Emerging transport behavior in manganites wires","authors":"T. Ward, Jian Shen","doi":"10.1109/ICSICT.2008.4734602","DOIUrl":"https://doi.org/10.1109/ICSICT.2008.4734602","url":null,"abstract":"The two hottest areas of research in condensed matter physics are complexity and nanoscale physics. Interestingly, these two areas have little overlap as most of the nanophysics research work is conducted using ¿simple¿ materials of metals or semiconductors instead of complex materials such as transition metal oxides. However, due to the strong electronic correlation, it is exactly the transition metal oxides that will most likely lead to observations of striking new phenomena under spatial confinement. We will use perovskite manganites as model systems to demonstrate how spatial confinement can dramatically affect their transport and magnetic properties. The emerging magnetic and transport behavior is likely associated with the electronic phase separation under confined geometry in the manganites. Some of the new properties such as ultrasharp jumps of magnetoresistance and reentrant metal-insulator transition may have significant impact on fabricating oxides-based novel devices.","PeriodicalId":436457,"journal":{"name":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121022044","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-30DOI: 10.1109/ICSICT.2008.4734728
K. Suemori, M. Taniguchi, T. Kamata
The influence of the dipole of an insulator surface on temporal changes in the source-drain current was investigated by using organic field-effect transistors with a surface-modified SiO2 insulator. The source-drain current decreased drastically with respect to time when the dipoles of the insulator surface displaced slightly. In order to obtain highly stable organic transistors, it is thus necessary to remove the mobile dipoles from the insulator surface.
{"title":"Instability for organic field effect transistors caused by dipole on insulator surface","authors":"K. Suemori, M. Taniguchi, T. Kamata","doi":"10.1109/ICSICT.2008.4734728","DOIUrl":"https://doi.org/10.1109/ICSICT.2008.4734728","url":null,"abstract":"The influence of the dipole of an insulator surface on temporal changes in the source-drain current was investigated by using organic field-effect transistors with a surface-modified SiO2 insulator. The source-drain current decreased drastically with respect to time when the dipoles of the insulator surface displaced slightly. In order to obtain highly stable organic transistors, it is thus necessary to remove the mobile dipoles from the insulator surface.","PeriodicalId":436457,"journal":{"name":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","volume":"153 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121312092","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-30DOI: 10.1109/ICSICT.2008.4734861
Dan Bao, Bo Xiang, Rui Shen, An Pan, Yun Chen, Xiao-yang Zeng
A 2304-bit flexible decoder for low-density parity-check (LDPC) codes is presented for Wireless-MAN applications. Based on modified turbo-decoding message-passing (M-TDMP) algorithm, the decoder achieves low complexity as well as fast convergence which produces high throughput of 138 Mbps working at 50 MHz. By adopting a novel scheme for early termination of iteration, the proposed decoder obtains large power efficiency. The decoder is implemented in SMIC 0.18 ¿m 1P6M CMOS technology, features a power dissipation of 179-mW operating at 50 MHz, and costs an area of 12.5 mm2.
{"title":"A 179-mW 2304-bit flexible LDPC decoder for Wireless-MAN applications","authors":"Dan Bao, Bo Xiang, Rui Shen, An Pan, Yun Chen, Xiao-yang Zeng","doi":"10.1109/ICSICT.2008.4734861","DOIUrl":"https://doi.org/10.1109/ICSICT.2008.4734861","url":null,"abstract":"A 2304-bit flexible decoder for low-density parity-check (LDPC) codes is presented for Wireless-MAN applications. Based on modified turbo-decoding message-passing (M-TDMP) algorithm, the decoder achieves low complexity as well as fast convergence which produces high throughput of 138 Mbps working at 50 MHz. By adopting a novel scheme for early termination of iteration, the proposed decoder obtains large power efficiency. The decoder is implemented in SMIC 0.18 ¿m 1P6M CMOS technology, features a power dissipation of 179-mW operating at 50 MHz, and costs an area of 12.5 mm2.","PeriodicalId":436457,"journal":{"name":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127075456","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-30DOI: 10.1109/ICSICT.2008.4734816
Zhiqun Cheng, Lingling Sun
A novel defected ground structure (DGS) is designed and applied to a flip-chip integrated millimeter wave oscillator. It is found that, when DGS is embedded in the resonant tank and the output terminal of an oscillator, the phase noise can be reduced and the output power is enhanced. Two oscillators with and without DGS are designed and compared. Measurement data shows that the phase noise of the oscillator with DGS is reduced by 4-6 dB, and the output power of the oscillator is increased by 0.8 dBm in comparison with the oscillator without DGS.
{"title":"Millimeter wave integrated oscillator with reduced phase noise and enhanced output power using a novel defected ground structure","authors":"Zhiqun Cheng, Lingling Sun","doi":"10.1109/ICSICT.2008.4734816","DOIUrl":"https://doi.org/10.1109/ICSICT.2008.4734816","url":null,"abstract":"A novel defected ground structure (DGS) is designed and applied to a flip-chip integrated millimeter wave oscillator. It is found that, when DGS is embedded in the resonant tank and the output terminal of an oscillator, the phase noise can be reduced and the output power is enhanced. Two oscillators with and without DGS are designed and compared. Measurement data shows that the phase noise of the oscillator with DGS is reduced by 4-6 dB, and the output power of the oscillator is increased by 0.8 dBm in comparison with the oscillator without DGS.","PeriodicalId":436457,"journal":{"name":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127115446","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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