{"title":"A Synthesis-based Bandwidth Enhancing Technique for CML Buffers/Amplifiers","authors":"Deyi Pi, Byung-Kwan Chun, P. Heydari","doi":"10.1109/CICC.2007.4405775","DOIUrl":null,"url":null,"abstract":"A synthesis-based bandwidth enhancing technique for current-mode-logic (CML) buffers/amplifiers is presented, which achieves bandwidth-enhancement-ratio (BWER) of 4.84, close to a proven theoretical upper limit of 4.93. By employing a complete step-by-step design methodology, the proposed technique can be applied to any load condition, which is characterized by the ratio between the load capacitance and the output capacitance of the transconductor cell. Several prototype buffer/amplifier circuits are designed using lower order passive networks to save chip area. The test chip is fabricated in a 0.18 mum CMOS process, and measurements show a BWER of 3.8.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"126 40","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 IEEE Custom Integrated Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.2007.4405775","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
A synthesis-based bandwidth enhancing technique for current-mode-logic (CML) buffers/amplifiers is presented, which achieves bandwidth-enhancement-ratio (BWER) of 4.84, close to a proven theoretical upper limit of 4.93. By employing a complete step-by-step design methodology, the proposed technique can be applied to any load condition, which is characterized by the ratio between the load capacitance and the output capacitance of the transconductor cell. Several prototype buffer/amplifier circuits are designed using lower order passive networks to save chip area. The test chip is fabricated in a 0.18 mum CMOS process, and measurements show a BWER of 3.8.
提出了一种基于综合的电流模式逻辑(CML)缓冲器/放大器带宽增强技术，该技术的带宽增强比(BWER)为4.84，接近已证实的理论上限4.93。通过采用完整的逐步设计方法，所提出的技术可以应用于任何负载条件，其特征是负载电容与transconductor电池输出电容之间的比率。为了节省芯片面积，采用低阶无源网络设计了几种原型缓冲/放大电路。测试芯片采用0.18 μ m CMOS工艺制造，测量结果显示BWER为3.8。
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