{"title":"A Time-Interleaved Track & hold in 0.13 μm CMOS sub-sampling a 4 GHz signal with 43 dB SNDR","authors":"S. Louwsma, E. V. Tuijl, M. Vertregt, B. Nauta","doi":"10.1109/CICC.2007.4405745","DOIUrl":null,"url":null,"abstract":"A 16-channel time-interleaved track and hold is presented. Three techniques are introduced enabling a high bandwidth and linearity and good timing alignment. Integrated ADCs are used to evaluate the performance of the T/H. Single channel performance is 43 dB SNDR at an input frequency of 4 GHz. Multi-channel performance is 48 dB SNDR at 1.35 GS/s with an ERBW of 1 GHz. The power consumption of the T/H including clock-driver and buffers is 74 mW.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"42 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"15","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 IEEE Custom Integrated Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.2007.4405745","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 15
Abstract
A 16-channel time-interleaved track and hold is presented. Three techniques are introduced enabling a high bandwidth and linearity and good timing alignment. Integrated ADCs are used to evaluate the performance of the T/H. Single channel performance is 43 dB SNDR at an input frequency of 4 GHz. Multi-channel performance is 48 dB SNDR at 1.35 GS/s with an ERBW of 1 GHz. The power consumption of the T/H including clock-driver and buffers is 74 mW.
提出了一种16通道时间交错跟踪和保持方法。介绍了实现高带宽、线性度和良好时序对准的三种技术。集成的adc用于评估温湿度的性能。在输入频率为4ghz时,单通道性能为43 dB SNDR。在1.35 GS/s下的多通道性能为48 dB SNDR, ERBW为1 GHz。包括时钟驱动器和缓冲器在内的温湿度功耗为74 mW。