{"title":"An Embedded 8-bit RISC Controller for Yield Enhancement of the 90-nm PRAM","authors":"Hyejung Kim, Kyomin Sohn, Jerald Yoo, H. Yoo","doi":"10.1109/CICC.2007.4405847","DOIUrl":null,"url":null,"abstract":"An embedded 8 b RISC for advanced memories is designed to control, analyze and optimize the memory timing and voltage parameters. The processor-based built-in-self-optimize (BISO) algorithm is proposed to enhance the memory yield. A test PRAM with the RISC is fabricated in 90 nm, 3-metal diode-switch process. By applying BISO, the PRAM margin window increases by 221%. It operates at 100 MHz and consumes 28.4 mW at 1.0 V supply voltage. The embedded RISC enables 100 Mb/s/pin read/write throughputs to PRAM.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"24 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 IEEE Custom Integrated Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.2007.4405847","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
An embedded 8 b RISC for advanced memories is designed to control, analyze and optimize the memory timing and voltage parameters. The processor-based built-in-self-optimize (BISO) algorithm is proposed to enhance the memory yield. A test PRAM with the RISC is fabricated in 90 nm, 3-metal diode-switch process. By applying BISO, the PRAM margin window increases by 221%. It operates at 100 MHz and consumes 28.4 mW at 1.0 V supply voltage. The embedded RISC enables 100 Mb/s/pin read/write throughputs to PRAM.
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