Pub Date : 2007-09-16DOI: 10.1109/CICC.2007.4405847
Hyejung Kim, Kyomin Sohn, Jerald Yoo, H. Yoo
An embedded 8 b RISC for advanced memories is designed to control, analyze and optimize the memory timing and voltage parameters. The processor-based built-in-self-optimize (BISO) algorithm is proposed to enhance the memory yield. A test PRAM with the RISC is fabricated in 90 nm, 3-metal diode-switch process. By applying BISO, the PRAM margin window increases by 221%. It operates at 100 MHz and consumes 28.4 mW at 1.0 V supply voltage. The embedded RISC enables 100 Mb/s/pin read/write throughputs to PRAM.
{"title":"An Embedded 8-bit RISC Controller for Yield Enhancement of the 90-nm PRAM","authors":"Hyejung Kim, Kyomin Sohn, Jerald Yoo, H. Yoo","doi":"10.1109/CICC.2007.4405847","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405847","url":null,"abstract":"An embedded 8 b RISC for advanced memories is designed to control, analyze and optimize the memory timing and voltage parameters. The processor-based built-in-self-optimize (BISO) algorithm is proposed to enhance the memory yield. A test PRAM with the RISC is fabricated in 90 nm, 3-metal diode-switch process. By applying BISO, the PRAM margin window increases by 221%. It operates at 100 MHz and consumes 28.4 mW at 1.0 V supply voltage. The embedded RISC enables 100 Mb/s/pin read/write throughputs to PRAM.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129781847","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-16DOI: 10.1109/CICC.2007.4405696
Sunyoung Kim, Seungjin Lee, Namjun Cho, Seong-Jun Song, H. Yoo
A real-time hearing aid chip with the reference ear model (REM) and the comparison processor (COMP) is proposed and implemented. Through the COMP the response differences between the reference ear model and the impaired ear of the patient are achieved and processed to compensate the hearing loss of the patient. By adopting this architecture, the fully internal gain fitting and verification of the hearing aid with only single initial hearing loss test is implemented. To reduce the power dissipation and achieve the high flexibility, the preamplifier which has programmable multi threshold voltages is introduced. The feedback controlled hearing aid chip is implemented in 0.18 mum CMOS technology, consumes less than 110 muW and has a die size of 3.7 mm2.
提出并实现了一种基于参考耳模型(REM)和比较处理器(COMP)的实时助听器芯片。通过COMP获得参考耳模型与患者受损耳之间的响应差异，并对其进行处理，以补偿患者的听力损失。采用该体系结构，只需进行一次初始听力损失测试，即可实现助听器的全内部增益拟合和验证。为了降低功耗和实现高灵活性，引入了可编程多阈值电压前置放大器。反馈控制助听器芯片采用0.18 μ m CMOS技术，功耗低于110 μ w，芯片尺寸为3.7 mm2。
{"title":"A Real-Time Feedback Controlled Hearing Aid Chip with Reference Ear Model","authors":"Sunyoung Kim, Seungjin Lee, Namjun Cho, Seong-Jun Song, H. Yoo","doi":"10.1109/CICC.2007.4405696","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405696","url":null,"abstract":"A real-time hearing aid chip with the reference ear model (REM) and the comparison processor (COMP) is proposed and implemented. Through the COMP the response differences between the reference ear model and the impaired ear of the patient are achieved and processed to compensate the hearing loss of the patient. By adopting this architecture, the fully internal gain fitting and verification of the hearing aid with only single initial hearing loss test is implemented. To reduce the power dissipation and achieve the high flexibility, the preamplifier which has programmable multi threshold voltages is introduced. The feedback controlled hearing aid chip is implemented in 0.18 mum CMOS technology, consumes less than 110 muW and has a die size of 3.7 mm2.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122151114","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-16DOI: 10.1109/CICC.2007.4405822
T. Phan, V. Krizhanovskii, Sang-Gug Lee
This paper presents an ultra low-power noncoherent transceiver (TRx) operating in 3-5 GHz band using energy detection (ED) receiver for impulse radio ultra-wideband (IR-UWB) systems. The proposed low-complexity ED receiver consists of a wideband LNA, a squarer, an analog integrator, and a sample and hold circuit, of which only the LNA consumes static current. The transmitter consists of a pulser which is based on the ON/OFF operation of an LC oscillator. Fabricated in 0.18-mum CMOS technology with 1.5 V supply, measurements show the FCC-compliant output pulses with the duration of 3.5 ns, which corresponds to 520 MHz bandwidth. Maximum pulse rate is up to over 200 MHz. The pulser dissipates only the dynamic current with average energy of 16.8 pJ per pulse, and the receiver dissipates 3.5 mA of static current. The receiver shows 9 dB of NF and a sensitivity of -70 dBm. Transceiver die size is 1.3times1 mm.
{"title":"Low-Power CMOS Energy Detection Transceiver for UWB Impulse Radio System","authors":"T. Phan, V. Krizhanovskii, Sang-Gug Lee","doi":"10.1109/CICC.2007.4405822","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405822","url":null,"abstract":"This paper presents an ultra low-power noncoherent transceiver (TRx) operating in 3-5 GHz band using energy detection (ED) receiver for impulse radio ultra-wideband (IR-UWB) systems. The proposed low-complexity ED receiver consists of a wideband LNA, a squarer, an analog integrator, and a sample and hold circuit, of which only the LNA consumes static current. The transmitter consists of a pulser which is based on the ON/OFF operation of an LC oscillator. Fabricated in 0.18-mum CMOS technology with 1.5 V supply, measurements show the FCC-compliant output pulses with the duration of 3.5 ns, which corresponds to 520 MHz bandwidth. Maximum pulse rate is up to over 200 MHz. The pulser dissipates only the dynamic current with average energy of 16.8 pJ per pulse, and the receiver dissipates 3.5 mA of static current. The receiver shows 9 dB of NF and a sensitivity of -70 dBm. Transceiver die size is 1.3times1 mm.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128507150","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-16DOI: 10.1109/CICC.2007.4405745
S. Louwsma, E. V. Tuijl, M. Vertregt, B. Nauta
A 16-channel time-interleaved track and hold is presented. Three techniques are introduced enabling a high bandwidth and linearity and good timing alignment. Integrated ADCs are used to evaluate the performance of the T/H. Single channel performance is 43 dB SNDR at an input frequency of 4 GHz. Multi-channel performance is 48 dB SNDR at 1.35 GS/s with an ERBW of 1 GHz. The power consumption of the T/H including clock-driver and buffers is 74 mW.
提出了一种16通道时间交错跟踪和保持方法。介绍了实现高带宽、线性度和良好时序对准的三种技术。集成的adc用于评估温湿度的性能。在输入频率为4ghz时，单通道性能为43 dB SNDR。在1.35 GS/s下的多通道性能为48 dB SNDR, ERBW为1 GHz。包括时钟驱动器和缓冲器在内的温湿度功耗为74 mW。
{"title":"A Time-Interleaved Track & hold in 0.13 μm CMOS sub-sampling a 4 GHz signal with 43 dB SNDR","authors":"S. Louwsma, E. V. Tuijl, M. Vertregt, B. Nauta","doi":"10.1109/CICC.2007.4405745","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405745","url":null,"abstract":"A 16-channel time-interleaved track and hold is presented. Three techniques are introduced enabling a high bandwidth and linearity and good timing alignment. Integrated ADCs are used to evaluate the performance of the T/H. Single channel performance is 43 dB SNDR at an input frequency of 4 GHz. Multi-channel performance is 48 dB SNDR at 1.35 GS/s with an ERBW of 1 GHz. The power consumption of the T/H including clock-driver and buffers is 74 mW.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127834151","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-16DOI: 10.1109/CICC.2007.4405769
Donghyun Kim, Kwanho Kim, Joo-Young Kim, Seungjin Lee, H. Yoo
An 81.6 GOPS object recognition processor is developed by using NoC and visual image processing (VIP) memory. SIFT (scale invariant feature transform) object recognition requires huge computing power and data transactions among tasks. The chip integrates 10 SIMD PEs for data/task level parallelism while the NoC facilitates inter-PE communications. The VIP memory searches local maximum pixel inside a 3times3 window in a single cycle providing 65.6 GOPS. The proposed processor achieves 15.9 fps SIFT feature extraction at 200 MHz.
{"title":"An 81.6 GOPS Object Recognition Processor Based on NoC and Visual Image Processing Memory","authors":"Donghyun Kim, Kwanho Kim, Joo-Young Kim, Seungjin Lee, H. Yoo","doi":"10.1109/CICC.2007.4405769","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405769","url":null,"abstract":"An 81.6 GOPS object recognition processor is developed by using NoC and visual image processing (VIP) memory. SIFT (scale invariant feature transform) object recognition requires huge computing power and data transactions among tasks. The chip integrates 10 SIMD PEs for data/task level parallelism while the NoC facilitates inter-PE communications. The VIP memory searches local maximum pixel inside a 3times3 window in a single cycle providing 65.6 GOPS. The proposed processor achieves 15.9 fps SIFT feature extraction at 200 MHz.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"2016 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127467968","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-16DOI: 10.1109/CICC.2007.4405798
Chang-Hyo Yu, Kyusik Chung, Donghyun Kim, L. Kim
In this paper, a power-efficient vertex processor with a geometry-specific arithmetic unit, vertex caches, and a vertex texturing unit is presented for mobile graphics environments. The arithmetic unit takes advantages of the geometry operations; a four-threaded and four-issue expanded VLIW datapath with a quad-float vertex texture fetcher. The vertex caches are optimized to acquire higher power efficiency. Moreover, an instruction-level power control method is adopted with an operand sharing and writeback re-allocation methods as well as operand isolations and gated clocks. The proposed vertex processor achieves 186 Mvertices/s of geometry performance which is 1.6 times faster than the previous results which adopt the IEEE754-compliant arithmetic units, and it supports OpenGL ES 2.0 and Vertex Shader Model 3.0. The processor is implemented in a 0.18-mum 1P4M CMOS process.
本文提出了一种具有几何特定运算单元、顶点缓存和顶点纹理单元的高效顶点处理器，用于移动图形环境。算术单元利用几何运算的优势;一个带有四浮点顶点纹理获取器的四线程和四问题扩展的VLIW数据路径。顶点缓存被优化以获得更高的功率效率。采用指令级功率控制方法，采用操作数共享和回写重分配方法以及操作数隔离和门控时钟。所提出的顶点处理器实现了186 Mvertices/s的几何性能，比之前采用ieee754算法单元的结果快1.6倍，并且支持OpenGL ES 2.0和vertex Shader Model 3.0。该处理器采用0.18 μ m 1P4M CMOS工艺实现。
{"title":"A 186Mvertices/s 161mW Floating-Point Vertex Processor for Mobile Graphics Systems","authors":"Chang-Hyo Yu, Kyusik Chung, Donghyun Kim, L. Kim","doi":"10.1109/CICC.2007.4405798","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405798","url":null,"abstract":"In this paper, a power-efficient vertex processor with a geometry-specific arithmetic unit, vertex caches, and a vertex texturing unit is presented for mobile graphics environments. The arithmetic unit takes advantages of the geometry operations; a four-threaded and four-issue expanded VLIW datapath with a quad-float vertex texture fetcher. The vertex caches are optimized to acquire higher power efficiency. Moreover, an instruction-level power control method is adopted with an operand sharing and writeback re-allocation methods as well as operand isolations and gated clocks. The proposed vertex processor achieves 186 Mvertices/s of geometry performance which is 1.6 times faster than the previous results which adopt the IEEE754-compliant arithmetic units, and it supports OpenGL ES 2.0 and Vertex Shader Model 3.0. The processor is implemented in a 0.18-mum 1P4M CMOS process.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"154 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131349944","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/CICC.2007.4405844
A. Papanikolaou, M. Corbalan, P. Marchal, B. Dierickx, F. Catthoor
Process variability is introducing uncertainty in all the system level parametric specifications. Existing variability aware techniques can only capture and model the variations on system timing and leakage power. This paper proposes a framework that can capture variability in the dynamic energy consumption as well. It percolates variability information from semiconductor process to the Register Transfer Level. This enables to capture the application dynamics and provide an accurate estimation of dynamic energy along with leakage and timing.
{"title":"At Tape-out: Can System Yield in Terms of Timing/Energy Specifications Be Predicted?","authors":"A. Papanikolaou, M. Corbalan, P. Marchal, B. Dierickx, F. Catthoor","doi":"10.1109/CICC.2007.4405844","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405844","url":null,"abstract":"Process variability is introducing uncertainty in all the system level parametric specifications. Existing variability aware techniques can only capture and model the variations on system timing and leakage power. This paper proposes a framework that can capture variability in the dynamic energy consumption as well. It percolates variability information from semiconductor process to the Register Transfer Level. This enables to capture the application dynamics and provide an accurate estimation of dynamic energy along with leakage and timing.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123110675","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/CICC.2007.4405750
H. Kodama, H. Okada, H. Ishikawa, Akio Tanaka
To relax the trade-off relationship between tuning range and phase noise, we have developed a new interpolative ring-VCO having a wide control voltage range over which frequency variation is linear. A wide lock-range, low phase noise PLL incorporating this VCO has been fabricated in a 90 nm CMOS process. It successfully operates at from 3.432 to 4.488 GHz (LF-mode) and from 6.600 to 9.240 GHz (HF-mode), with 528 MHz spacing, while drawing 30 to 37 mA from a 1.5 V supply. Measured integrated phase noise is below a targeted 4 degrees in both modes when the reference frequency is 264 MHz and less than 4 degrees in the LF-mode when it is 66 MHz.
{"title":"Wide Lock-Range, Low Phase-Noise PLL using Interpolative Ring-VCO with Coarse Frequency Tuning and Frequency Linearization","authors":"H. Kodama, H. Okada, H. Ishikawa, Akio Tanaka","doi":"10.1109/CICC.2007.4405750","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405750","url":null,"abstract":"To relax the trade-off relationship between tuning range and phase noise, we have developed a new interpolative ring-VCO having a wide control voltage range over which frequency variation is linear. A wide lock-range, low phase noise PLL incorporating this VCO has been fabricated in a 90 nm CMOS process. It successfully operates at from 3.432 to 4.488 GHz (LF-mode) and from 6.600 to 9.240 GHz (HF-mode), with 528 MHz spacing, while drawing 30 to 37 mA from a 1.5 V supply. Measured integrated phase noise is below a targeted 4 degrees in both modes when the reference frequency is 264 MHz and less than 4 degrees in the LF-mode when it is 66 MHz.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125129009","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/CICC.2007.4405715
N. Yoshii, K. Mizutani, Y. Sugimoto
A 2 V, 25 MS/s, current-mode and pipelined analog-to-digital converter (ADC) which realizes a 1.5-bit bit-block architecture and uses a front-end current-mode sample-and-hold (S/H) circuit is described. In order to obtain the precise output current without suffering from poor current mismatch in a bit-block, the input and output currents in a current-mirror circuit are exchanged at every clock period. This produces signal currents at the output of a bit-block with positive and negative mismatch errors in turn. Since the analog-to-digital (A-D) converted digital codes of a bit-block contain these positive and negative mismatch errors, the errors are canceled out by taking the average of the consecutive digital codes at the output part of the ADC. A current-mode ADC using this proposed scheme has been fabricated by using 0.25 mum CMOS devices. The results show that the effective number of bits (ENOB) is 7.6, that the spurious-free dynamic range (SFDR) is 48 dB, with a 20 MHz clock from a 2 V supply voltage.
{"title":"A Current-mode ADC with Current Exchanging and Averaging Capabilities by Switching the Currents and Calculating Data in the Digital Domain","authors":"N. Yoshii, K. Mizutani, Y. Sugimoto","doi":"10.1109/CICC.2007.4405715","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405715","url":null,"abstract":"A 2 V, 25 MS/s, current-mode and pipelined analog-to-digital converter (ADC) which realizes a 1.5-bit bit-block architecture and uses a front-end current-mode sample-and-hold (S/H) circuit is described. In order to obtain the precise output current without suffering from poor current mismatch in a bit-block, the input and output currents in a current-mirror circuit are exchanged at every clock period. This produces signal currents at the output of a bit-block with positive and negative mismatch errors in turn. Since the analog-to-digital (A-D) converted digital codes of a bit-block contain these positive and negative mismatch errors, the errors are canceled out by taking the average of the consecutive digital codes at the output part of the ADC. A current-mode ADC using this proposed scheme has been fabricated by using 0.25 mum CMOS devices. The results show that the effective number of bits (ENOB) is 7.6, that the spurious-free dynamic range (SFDR) is 48 dB, with a 20 MHz clock from a 2 V supply voltage.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126043859","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/CICC.2007.4405778
A. Amirkhany, A. Abbasfar, J. Savoj, M. Horowitz
Many wideband circuits use interleaving to extend bandwidth leaving them with a cyclically time-variant output. This paper describes a technique for characterization of these types of circuits based on least-squares estimation of the time-varying response of circuits. Applying the methodology to a 90-nm, 12-GS/s 8-bit digitally-equalized DAC, shows significant timing varying behavior. Furthermore, using the data obtained from characterization to construct linear time-variant compensation improves the DAC signal-to-distortion ratio by at least 6 dB.
{"title":"Time-Variant Characterization and Compensation of Wideband Circuits","authors":"A. Amirkhany, A. Abbasfar, J. Savoj, M. Horowitz","doi":"10.1109/CICC.2007.4405778","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405778","url":null,"abstract":"Many wideband circuits use interleaving to extend bandwidth leaving them with a cyclically time-variant output. This paper describes a technique for characterization of these types of circuits based on least-squares estimation of the time-varying response of circuits. Applying the methodology to a 90-nm, 12-GS/s 8-bit digitally-equalized DAC, shows significant timing varying behavior. Furthermore, using the data obtained from characterization to construct linear time-variant compensation improves the DAC signal-to-distortion ratio by at least 6 dB.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126661645","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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