S. Veeramachaneni, M. K. Adimulam, V. Tummala, M. Srinivas
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引用次数: 28
Abstract
In this paper, a low power and variable resolution (adaptive) flash ADC is proposed. The ADC enables exponential power reduction while the reduction in resolution is linear. In the proposed design, unused parallel voltage comparators are switched to standby mode leading to consumption of only the leakage power. The ADC, capable of operating at 4-bit, 5-bit, and 6-bit precision, dissipates 6mW at 4-bit and 12mW at 6-bit, and operates at a sampling frequency of 1 to 2 GSPS. The ADC has been designed and simulated in standard 65nm CMOS technology using Cadence tools
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