Pub Date : 2009-01-19DOI: 10.1109/VLSI.Design.2009.105
R. Aitken
CMOS scaling has led to ever-increasing numbers of potentially available transistors on chips. At the same time, design productivity has also continued to improve, but has not been able to keep up, resulting in increasing design effort. Many factors contribute to this situation, but one key element is the complexity involved in ensuring that yield targets will be met. (DFY). This talk outlines the basics of design-for-yield (DFY) and shows how it relates to design-for-manufacturability, test, and variability (DFM, DFT, and DFV respectively). It is shown how a comprehensive approach to all of the problems, known as DFX, can lead to improved design methodology and hence improved productivity.
{"title":"DFX and Productivity","authors":"R. Aitken","doi":"10.1109/VLSI.Design.2009.105","DOIUrl":"https://doi.org/10.1109/VLSI.Design.2009.105","url":null,"abstract":"CMOS scaling has led to ever-increasing numbers of potentially available transistors on chips. At the same time, design productivity has also continued to improve, but has not been able to keep up, resulting in increasing design effort. Many factors contribute to this situation, but one key element is the complexity involved in ensuring that yield targets will be met. (DFY). This talk outlines the basics of design-for-yield (DFY) and shows how it relates to design-for-manufacturability, test, and variability (DFM, DFT, and DFV respectively). It is shown how a comprehensive approach to all of the problems, known as DFX, can lead to improved design methodology and hence improved productivity.","PeriodicalId":267121,"journal":{"name":"2009 22nd International Conference on VLSI Design","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-01-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124828015","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-01-05DOI: 10.1109/VLSI.Design.2009.14
R. Thakker, M. Baghini, M. Patil
This paper presents application and effectiveness of Hierarchical particle swarm optimization (HPSO) algorithm for automatic sizing of low-power analog circuits. For the purpose of comparison, circuits are also designed using PSO and Genetic Algorithm (GA). CMOS technologies from 0.35 µm down to 0.13 µm are used. PVT (process, voltage, temperature) variations are considered during the design of circuits. We show that HPSO algorithm converges to a better solution, compared to PSO and GA. For CMOS Miller OTA, even performance of the circuit designed by HPSO algorithm is better than the performance of recently reported manually designed circuit. For the first time, design of this OTA, in 0.4 V supply voltage, is also presented. For this new design, HPSO algorithm has taken 23.5 minutes of CPU time on a Sun system with1.2 GHz processor and 8 GB RAM.
本文介绍了层次粒子群优化算法在低功耗模拟电路自动尺寸设计中的应用及其有效性。为了比较，还采用粒子群算法和遗传算法设计了电路。从0.35µm到0.13µm的CMOS技术被使用。PVT(过程、电压、温度)变化在电路设计中被考虑。我们证明了与粒子群算法和遗传算法相比，HPSO算法收敛到一个更好的解。对于CMOS Miller OTA而言，采用HPSO算法设计的电路的均匀性能优于最近报道的人工设计电路的性能。本文还首次提出了在0.4 V电源电压下的OTA设计。对于这种新设计，在具有1.2 GHz处理器和8gb RAM的Sun系统上，HPSO算法占用了23.5分钟的CPU时间。
{"title":"Low-Power Low-Voltage Analog Circuit Design Using Hierarchical Particle Swarm Optimization","authors":"R. Thakker, M. Baghini, M. Patil","doi":"10.1109/VLSI.Design.2009.14","DOIUrl":"https://doi.org/10.1109/VLSI.Design.2009.14","url":null,"abstract":"This paper presents application and effectiveness of Hierarchical particle swarm optimization (HPSO) algorithm for automatic sizing of low-power analog circuits. For the purpose of comparison, circuits are also designed using PSO and Genetic Algorithm (GA). CMOS technologies from 0.35 µm down to 0.13 µm are used. PVT (process, voltage, temperature) variations are considered during the design of circuits. We show that HPSO algorithm converges to a better solution, compared to PSO and GA. For CMOS Miller OTA, even performance of the circuit designed by HPSO algorithm is better than the performance of recently reported manually designed circuit. For the first time, design of this OTA, in 0.4 V supply voltage, is also presented. For this new design, HPSO algorithm has taken 23.5 minutes of CPU time on a Sun system with1.2 GHz processor and 8 GB RAM.","PeriodicalId":267121,"journal":{"name":"2009 22nd International Conference on VLSI Design","volume":"151 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-01-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115563036","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-01-05DOI: 10.1109/VLSI.Design.2009.104
G. Delp
For decades designers have worked with the digital abstraction, signals are either logical true or logical false. As with all abstractions, this one had great utility, allowed optimizations in analysis, and separated two areas of difficult analysis, making the design task achievable. In 2009, this abstraction becomes more valuable, and more complex. Parts of digital circuits will be turned off relative to other parts, parts will enjoy low-power slow-down modes, and parts will scream with performance and energy. The good news is that there is a simple way to express the relationships, boundaries, activities, and side effects of many power domains without having to give up most of the simplifications that the digital abstraction allow us. The bad news is that there are currently two ways to do it. Using examples from a number of design flows and design problems, the speaker will show how to use both UPF/P1801 and CPF to express the power constraints and characteristics of designs. As work is ongoing in both the Si2 Low Power Coalition, and the IEEE P1801 groups, the January state of interoperability will be greater than it is currently, and much quicker and cleaner to hear about than it has been to develop.
{"title":"Making Sense Out of the Potential Babble of Low Power Standards","authors":"G. Delp","doi":"10.1109/VLSI.Design.2009.104","DOIUrl":"https://doi.org/10.1109/VLSI.Design.2009.104","url":null,"abstract":"For decades designers have worked with the digital abstraction, signals are either logical true or logical false. As with all abstractions, this one had great utility, allowed optimizations in analysis, and separated two areas of difficult analysis, making the design task achievable. In 2009, this abstraction becomes more valuable, and more complex. Parts of digital circuits will be turned off relative to other parts, parts will enjoy low-power slow-down modes, and parts will scream with performance and energy. The good news is that there is a simple way to express the relationships, boundaries, activities, and side effects of many power domains without having to give up most of the simplifications that the digital abstraction allow us. The bad news is that there are currently two ways to do it. Using examples from a number of design flows and design problems, the speaker will show how to use both UPF/P1801 and CPF to express the power constraints and characteristics of designs. As work is ongoing in both the Si2 Low Power Coalition, and the IEEE P1801 groups, the January state of interoperability will be greater than it is currently, and much quicker and cleaner to hear about than it has been to develop.","PeriodicalId":267121,"journal":{"name":"2009 22nd International Conference on VLSI Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-01-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129357595","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-01-05DOI: 10.1109/VLSI.Design.2009.48
N. Chandra, Apoorva Kumar Yati, A. Bhattacharyya
In this paper an extension of the Sakurai and Newton's Nth power law model, namely Extended-Sakurai-Newton Model, is proposed. The proposed model (henceforth referred to as the ESN model) preserves the simplicity and accuracy of the Sakurai Newton model for the estimation of drain current in deep submicron CMOS devices and extends it for varying device widths. Although the Modified Sakurai-Newton Current Model (MSN Model) also provides an estimation of transistor drain current with varying transistor widths, it suffers from the drawback of being more error prone and computation intensive in parameter extraction. The proposed model matches with BSIM3v3 level 49 T-SPICE simulations to within an error of 1.8%(3.67% maximum), in 0.18µm and 0.25µm CMOS processes for a wide range of transistor widths and input rise/fall times. The proposed model is further used to improve the Elmore Delay prediction of CMOS inverter operated at low supply voltages. The centroid-of-current and power based delay metrics [1] are modified based on the proposed model. The new delay metric is able to accurately predict the delay of CMOS inverter operated at low supply voltages. The proposed ESN Model is also applied to predict the delay of two-input CMOS NAND gate. Hence the proposed model can be effectively used in the design of digital CMOS gates involving varying device widths and supply voltages in the deep submicron region.
{"title":"Extended-Sakurai-Newton MOSFET Model for Ultra-Deep-Submicrometer CMOS Digital Design","authors":"N. Chandra, Apoorva Kumar Yati, A. Bhattacharyya","doi":"10.1109/VLSI.Design.2009.48","DOIUrl":"https://doi.org/10.1109/VLSI.Design.2009.48","url":null,"abstract":"In this paper an extension of the Sakurai and Newton's Nth power law model, namely Extended-Sakurai-Newton Model, is proposed. The proposed model (henceforth referred to as the ESN model) preserves the simplicity and accuracy of the Sakurai Newton model for the estimation of drain current in deep submicron CMOS devices and extends it for varying device widths. Although the Modified Sakurai-Newton Current Model (MSN Model) also provides an estimation of transistor drain current with varying transistor widths, it suffers from the drawback of being more error prone and computation intensive in parameter extraction. The proposed model matches with BSIM3v3 level 49 T-SPICE simulations to within an error of 1.8%(3.67% maximum), in 0.18µm and 0.25µm CMOS processes for a wide range of transistor widths and input rise/fall times. The proposed model is further used to improve the Elmore Delay prediction of CMOS inverter operated at low supply voltages. The centroid-of-current and power based delay metrics [1] are modified based on the proposed model. The new delay metric is able to accurately predict the delay of CMOS inverter operated at low supply voltages. The proposed ESN Model is also applied to predict the delay of two-input CMOS NAND gate. Hence the proposed model can be effectively used in the design of digital CMOS gates involving varying device widths and supply voltages in the deep submicron region.","PeriodicalId":267121,"journal":{"name":"2009 22nd International Conference on VLSI Design","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-01-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124679532","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-01-05DOI: 10.1109/VLSI.Design.2009.60
H. Yotsuyanagi, M. Hashizume, Toshiyuki Tsutsumi, K. Yamazaki, T. Aikyo, Y. Higami, Hiroshi Takahashi, Y. Takamatsu
Open faults are difficult to test since the voltage at the floating line is unpredicted and depends on the voltage at the adjacent lines. The modeling for open faults with considering adjacent lines has been proposed in [10]. In this work, the 90 nm IC is designed and fabricated to evaluate how the voltage at adjacent lines affect the defective line. The open fault macros with a transmission gate and with an intentional break are included in the IC. The nine lines are placed in parallel in three layers to observe the effect of the coupling capacitance when an open occurs. The benchmark circuits with the open fault macro are also included in the IC. The simulation and experimental results show that the relationship between the floating line and the adjacent lines. The experimental results are also compared with the open fault model that calculate the weighted sum of voltages at the adjacent lines.
{"title":"Fault Effect of Open Faults Considering Adjacent Signal Lines in a 90 nm IC","authors":"H. Yotsuyanagi, M. Hashizume, Toshiyuki Tsutsumi, K. Yamazaki, T. Aikyo, Y. Higami, Hiroshi Takahashi, Y. Takamatsu","doi":"10.1109/VLSI.Design.2009.60","DOIUrl":"https://doi.org/10.1109/VLSI.Design.2009.60","url":null,"abstract":"Open faults are difficult to test since the voltage at the floating line is unpredicted and depends on the voltage at the adjacent lines. The modeling for open faults with considering adjacent lines has been proposed in [10]. In this work, the 90 nm IC is designed and fabricated to evaluate how the voltage at adjacent lines affect the defective line. The open fault macros with a transmission gate and with an intentional break are included in the IC. The nine lines are placed in parallel in three layers to observe the effect of the coupling capacitance when an open occurs. The benchmark circuits with the open fault macro are also included in the IC. The simulation and experimental results show that the relationship between the floating line and the adjacent lines. The experimental results are also compared with the open fault model that calculate the weighted sum of voltages at the adjacent lines.","PeriodicalId":267121,"journal":{"name":"2009 22nd International Conference on VLSI Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-01-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130568499","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-01-05DOI: 10.1109/VLSI.Design.2009.50
L. Manojkumar, A. Mohan, N. Krishnapura
Two methods for generating in phase and quadrature local oscillator signals at 2.4GHz for Zigbee transceivers are investigated. In one method, the output of a 4.8GHz LC VCO is divided by two to obtain I and Q phases at 2.4GHz. In another method, outputs of a four stage differential ring VCO at 1.2GHz are appropriately multiplied to obtain I and Q phases at 2.4GHz. These circuits are designed and laid out in a 0.18 µm CMOS process and they operate from a 1.8V power supply. The former architecture occupies 0.052mm2, consumes7.56mW, and has a phase noise of -117 dBc/Hz at 3.5MHz. The latter occupies 0.021mm2, consumes 9mW, and has a phase noise of -97 dBc/Hz at 3.5MHz. Temperature variations of the ring oscillator are minimized using a combination of constant current and constant g_m biasing.
研究了产生2.4GHz同相和正交本振信号的两种方法。其中一种方法是将4.8GHz LC压控振荡器的输出除以2，得到2.4GHz的I相和Q相。在另一种方法中，将1.2GHz的四级差分环压控振荡器的输出适当相乘，得到2.4GHz的I相和Q相。这些电路采用0.18 μ m CMOS工艺设计和布局，工作电源为1.8V。前一种架构占地0.052mm2，功耗7.56 mw, 3.5MHz时相位噪声为-117 dBc/Hz。后者占用0.021mm2，消耗9mW，在3.5MHz时相位噪声为-97 dBc/Hz。环形振荡器的温度变化使用恒定电流和恒定g_m偏置的组合最小化。
{"title":"A Comparison of Approaches to Carrier Generation for Zigbee Transceivers","authors":"L. Manojkumar, A. Mohan, N. Krishnapura","doi":"10.1109/VLSI.Design.2009.50","DOIUrl":"https://doi.org/10.1109/VLSI.Design.2009.50","url":null,"abstract":"Two methods for generating in phase and quadrature local oscillator signals at 2.4GHz for Zigbee transceivers are investigated. In one method, the output of a 4.8GHz LC VCO is divided by two to obtain I and Q phases at 2.4GHz. In another method, outputs of a four stage differential ring VCO at 1.2GHz are appropriately multiplied to obtain I and Q phases at 2.4GHz. These circuits are designed and laid out in a 0.18 µm CMOS process and they operate from a 1.8V power supply. The former architecture occupies 0.052mm2, consumes7.56mW, and has a phase noise of -117 dBc/Hz at 3.5MHz. The latter occupies 0.021mm2, consumes 9mW, and has a phase noise of -97 dBc/Hz at 3.5MHz. Temperature variations of the ring oscillator are minimized using a combination of constant current and constant g_m biasing.","PeriodicalId":267121,"journal":{"name":"2009 22nd International Conference on VLSI Design","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-01-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121381801","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-01-05DOI: 10.1109/VLSI.Design.2009.69
S. Srinivasan, S. Mathew, V. Erraguntla, R. Krishnamurthy
This paper describes an all-digital on-die true random number generator implemented in 45nm CMOS technology, with random bit throughput of 4Gbps and total energy consumption of 0.57pJ/bit. A 2-step tuning mechanism enables robust operation in the presence of up to 20% fabrication-time process variation as well as immunity to run-time voltage and temperature fluctuation. The 100% use of digital components enables a compact layout occupying 1024µm^2 with high entropy/bit of 0.94, and scalable operation down to 0.5V, while passing all NIST RNG tests.
{"title":"A 4Gbps 0.57pJ/bit Process-Voltage-Temperature Variation Tolerant All-Digital True Random Number Generator in 45nm CMOS","authors":"S. Srinivasan, S. Mathew, V. Erraguntla, R. Krishnamurthy","doi":"10.1109/VLSI.Design.2009.69","DOIUrl":"https://doi.org/10.1109/VLSI.Design.2009.69","url":null,"abstract":"This paper describes an all-digital on-die true random number generator implemented in 45nm CMOS technology, with random bit throughput of 4Gbps and total energy consumption of 0.57pJ/bit. A 2-step tuning mechanism enables robust operation in the presence of up to 20% fabrication-time process variation as well as immunity to run-time voltage and temperature fluctuation. The 100% use of digital components enables a compact layout occupying 1024µm^2 with high entropy/bit of 0.94, and scalable operation down to 0.5V, while passing all NIST RNG tests.","PeriodicalId":267121,"journal":{"name":"2009 22nd International Conference on VLSI Design","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-01-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116509855","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-01-05DOI: 10.1109/VLSI.Design.2009.117
A. Pal, S. Chattopadhyay
In recent years, power dissipation has emerged as the key issue not only for portable computers and mobile communication devices, but also for high-end systems. Reducing power dissipation is of primary importance in achieving longer battery life in portable devices. On the other hand, for high-end systems the cooling and packaging requirements are pushing the chip designers for low power alternatives. As a consequence, apart from the size, cost and performance, now-adays power is also considered as one of the most important constraints. This has led to vigorous research in the synthesis of low-power and high-performance circuits and systems. Moreover, aggressive device size scaling used to achieve high-performance leads to increased variability due to short-channel and other effects. This, in turn, leads to variations in process parameters such as, Leff, Nch, W, Tox, Vt, etc. Performance parameters such as power and delay are significantly affected due to the variations in process parameters and environmental/operational (Vdd, temperature, input values, etc.) conditions. Due to variability, the design methodology in the future nanometer VLSI circuits will essentially require a paradigm shift from deterministic to probabilistic and statistical design approach. The tight constraint on power dissipation has also created new challenges for testing low power VLSI circuits, as the traditional test techniques do not account for power dissipation during test application. It is now an accepted truth that test power is often much higher than the power consumed in normal operation, due to voluminous test data, test parallelization and the low correlation between successive test patterns. The objective of this tutorial is to provide an overview of different aspects of low power circuit synthesis at various levels of design hierarchy. It will introduce techniques to optimize the performance and power in the presence of process variations. Low power testing techniques will also be discussed.
{"title":"Synthesis & Testing for Low Power","authors":"A. Pal, S. Chattopadhyay","doi":"10.1109/VLSI.Design.2009.117","DOIUrl":"https://doi.org/10.1109/VLSI.Design.2009.117","url":null,"abstract":"In recent years, power dissipation has emerged as the key issue not only for portable computers and mobile communication devices, but also for high-end systems. Reducing power dissipation is of primary importance in achieving longer battery life in portable devices. On the other hand, for high-end systems the cooling and packaging requirements are pushing the chip designers for low power alternatives. As a consequence, apart from the size, cost and performance, now-adays power is also considered as one of the most important constraints. This has led to vigorous research in the synthesis of low-power and high-performance circuits and systems. Moreover, aggressive device size scaling used to achieve high-performance leads to increased variability due to short-channel and other effects. This, in turn, leads to variations in process parameters such as, Leff, Nch, W, Tox, Vt, etc. Performance parameters such as power and delay are significantly affected due to the variations in process parameters and environmental/operational (Vdd, temperature, input values, etc.) conditions. Due to variability, the design methodology in the future nanometer VLSI circuits will essentially require a paradigm shift from deterministic to probabilistic and statistical design approach. The tight constraint on power dissipation has also created new challenges for testing low power VLSI circuits, as the traditional test techniques do not account for power dissipation during test application. It is now an accepted truth that test power is often much higher than the power consumed in normal operation, due to voluminous test data, test parallelization and the low correlation between successive test patterns. The objective of this tutorial is to provide an overview of different aspects of low power circuit synthesis at various levels of design hierarchy. It will introduce techniques to optimize the performance and power in the presence of process variations. Low power testing techniques will also be discussed.","PeriodicalId":267121,"journal":{"name":"2009 22nd International Conference on VLSI Design","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-01-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114832488","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-01-05DOI: 10.1109/VLSI.Design.2009.26
Soumya Pandit, C. Mandal, A. Patra
This paper presents a systematic methodology for construction of high-level performance models using least squares support vector machine. The transistor sizes of the circuit-level implementation of a component block along with a set of geometry constraints applied over them define the sample space. Optimal values of the model hyper parameters are computed using genetic algorithm. The novelty of the methodology is that the models constructed with this methodology are accurate, fast to evaluate with good generalization ability and low construction time. The present methodology has been compared with two other standard methodologies and the novelties are clearly demonstrated with experimental results.
{"title":"Systematic Methodology for High-Level Performance Modeling of Analog Systems","authors":"Soumya Pandit, C. Mandal, A. Patra","doi":"10.1109/VLSI.Design.2009.26","DOIUrl":"https://doi.org/10.1109/VLSI.Design.2009.26","url":null,"abstract":"This paper presents a systematic methodology for construction of high-level performance models using least squares support vector machine. The transistor sizes of the circuit-level implementation of a component block along with a set of geometry constraints applied over them define the sample space. Optimal values of the model hyper parameters are computed using genetic algorithm. The novelty of the methodology is that the models constructed with this methodology are accurate, fast to evaluate with good generalization ability and low construction time. The present methodology has been compared with two other standard methodologies and the novelties are clearly demonstrated with experimental results.","PeriodicalId":267121,"journal":{"name":"2009 22nd International Conference on VLSI Design","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-01-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122283002","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-01-05DOI: 10.1109/VLSI.Design.2009.113
Anmol Mathur, Qi Wang
Power reduction is becoming a critical design criterion for ASIC/SOC designers. Reducing both dynamic and leakage power is imperative to meet power budgets for portable devices as well as to ensure that the systems that these ASICs meet their packaging and cooling costs. In addition, the power of an ASIC has a significant impact on its reliability and manufacturing yield. Traditionally, most automated power optimization tools have focused at gate-level and physical level optimizations. However, major power reductions are only possible by addressing power at the RTL and system levels. At these levels, it is possible to make the sequential modifications needed to reduce power and energy consumption via techniques like sequential clock gating, power gating, voltage/frequency scaling and other micro-architectural techniques. The focus of this tutorial will be on techniques for power reduction at the RTL and system level. It will also focus on expressing power intent at system and RTL levels and the flows needed to use that power intent in tools for functional verification, RTL-level optimization, logic synthesis and physical design. The following sections describe the key focus areas in the tutorial. We will start by discussing the key trends in the semiconductor industry and in CMOS technology and relate them to the need for power-aware design flows all the way from systemlevel design, through micro-architecture definition and RTL design and implementation. We will then present different power and energy metrics that are used at different points in the design cycle and for different purposes such as average power of a system, peak power of a system, energy per cycle etc. We will relate these metrics to their typical use and discuss when a metric should be used and optimized. State-of–the-art techniques for estimation of power and energy metrics will be presented including those for software power estimation, energy estimation for applications on a system, RTL and gate-level power estimation etc. We will discuss both simulation-based and statistical techniques for estimating switching activity in a design. Since, creation of system-level models is becoming a standard part of the design flow in most design teams, we will present typical flows from system-level models to RTL and the kinds of power/energy tradeoffs done at these levels such as power islands and mode identification, memory and bus architectures, voltage scaling and scheduling, and identification of clocking schemes and clock domains. Since power of a design is a function of how it performs a computation over time, almost all the major transformations that have significant impact on the power of a design are sequential in nature – they change the sequence of values generated at key internal registers or memories in time. We will discuss the sequential optimizations like, sequential clock gating, power gating, dynamic voltage scaling and memory banking. The impact of these optimizations on
{"title":"Power Reduction Techniques and Flows at RTL and System Level","authors":"Anmol Mathur, Qi Wang","doi":"10.1109/VLSI.Design.2009.113","DOIUrl":"https://doi.org/10.1109/VLSI.Design.2009.113","url":null,"abstract":"Power reduction is becoming a critical design criterion for ASIC/SOC designers. Reducing both dynamic and leakage power is imperative to meet power budgets for portable devices as well as to ensure that the systems that these ASICs meet their packaging and cooling costs. In addition, the power of an ASIC has a significant impact on its reliability and manufacturing yield. Traditionally, most automated power optimization tools have focused at gate-level and physical level optimizations. However, major power reductions are only possible by addressing power at the RTL and system levels. At these levels, it is possible to make the sequential modifications needed to reduce power and energy consumption via techniques like sequential clock gating, power gating, voltage/frequency scaling and other micro-architectural techniques. The focus of this tutorial will be on techniques for power reduction at the RTL and system level. It will also focus on expressing power intent at system and RTL levels and the flows needed to use that power intent in tools for functional verification, RTL-level optimization, logic synthesis and physical design. The following sections describe the key focus areas in the tutorial. We will start by discussing the key trends in the semiconductor industry and in CMOS technology and relate them to the need for power-aware design flows all the way from systemlevel design, through micro-architecture definition and RTL design and implementation. We will then present different power and energy metrics that are used at different points in the design cycle and for different purposes such as average power of a system, peak power of a system, energy per cycle etc. We will relate these metrics to their typical use and discuss when a metric should be used and optimized. State-of–the-art techniques for estimation of power and energy metrics will be presented including those for software power estimation, energy estimation for applications on a system, RTL and gate-level power estimation etc. We will discuss both simulation-based and statistical techniques for estimating switching activity in a design. Since, creation of system-level models is becoming a standard part of the design flow in most design teams, we will present typical flows from system-level models to RTL and the kinds of power/energy tradeoffs done at these levels such as power islands and mode identification, memory and bus architectures, voltage scaling and scheduling, and identification of clocking schemes and clock domains. Since power of a design is a function of how it performs a computation over time, almost all the major transformations that have significant impact on the power of a design are sequential in nature – they change the sequence of values generated at key internal registers or memories in time. We will discuss the sequential optimizations like, sequential clock gating, power gating, dynamic voltage scaling and memory banking. The impact of these optimizations on","PeriodicalId":267121,"journal":{"name":"2009 22nd International Conference on VLSI Design","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-01-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131919791","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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