A Q-Band Amplifier Implemented with Stacked 45-nm CMOS FETs

2011 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS) Pub Date : 2011-11-01 DOI:10.1109/CSICS.2011.6062465

S. Pornpromlikit, H. Dabag, B. Hanafi, Joohwa Kim, L. Larson, J. Buckwalter, P. Asbeck

引用次数: 53

Abstract

A stacked FET, single-stage 45-GHz (Q-band) CMOS power amplifier (PA) is presented. The design stacked three FETs to avoid breakdown while allowing a high supply voltage. The IC was implemented in a 45-nm CMOS SOI process. The saturated output power exceeds 18 dBm from a 4-V supply. Integrated shielded coplanar waveguide (CPW) transmission lines as well as metal finger capacitors were used for input and output matching. The amplifier occupies an area of 450x500 im² including pads, while achieving a maximum power-added-efficiency (PAE) above 20%.

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用45纳米CMOS场效应管实现的q波段放大器

提出了一种单级45 ghz (q波段)CMOS功率放大器(PA)。该设计将三个场效应管堆叠以避免击穿，同时允许高电源电压。该集成电路采用45纳米CMOS SOI工艺实现。4v电源的饱和输出功率超过18dbm。采用集成屏蔽共面波导(CPW)传输线和金属指电容进行输入输出匹配。该放大器的面积为450 × 500 m²(包括焊盘)，同时实现了20%以上的最大功率附加效率(PAE)。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2011 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)

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