A Reliability Enhanced 5nm CMOS Technology Featuring 5th Generation FinFET with Fully-Developed EUV and High Mobility Channel for Mobile SoC and High Performance Computing Application

Abstract

To keep up with the dominance in the field of leading semiconductor technology innovation, TSMC has announced the risk production of its most advanced 5nm CMOS logic node [1] using the full-fledged EUV and high mobility channel (HMC) FinFETs. Supporting the state of the art mobile SOC chips and HPC application needs, this 5nm technology node provides ~1.8x improvement in logic density, 15% speed gain and 30% power reduction as compared to its previous 7nm generation [1] - [2] . This paper, for the first time, brings out the detailed reliability attributes for the TSMC 5nm technology node from the device to various chip/package level reliability testing. While delivering an enhanced performance for N5, here we demonstrate the reliability benefit in terms of Bias Temperature Instability (BTI), Hot Carrier Degradation (HCD), Time dependent dielectric breakdown (TDDB) degradation modes in device level. Not only that, N5 node also delivers excellent reliability margins in chip level evaluations for SRAM and logic CPU/GPU applications. Moreover, to compete with the strictest industry reliability requirements even to the DPPM or low DPPB levels, N5 logic confirms its benefit for the automotive applications.