Pub Date : 2020-12-12DOI: 10.1109/IEDM13553.2020.9372094
Cheng-Lin Sung, H. Lue, M. Wei, S. Ho, Han-Wen Hu, P. Du, Wei-Chen Chen, C. Lo, T. Yeh, Keh-Chung Wang, Chih-Yuan Lu
The analog neuromorphic circuits with functional memory devices are considered as an ultimate ideal approach to mimic the human brain for artificial intelligence (AI). The spiking neural network (SNN) with integrate-and-fire (IF) circuit is the classic building block theoretically, but so far it is very difficult to find ideal devices to realize the SNN circuit. In this work, we propose a novel functional memory that is enabled by a novel thyristor, which features super-steep slope (S.S.~0.015mV/dec), large ON/OFF ratio (> 5 orders), and tunable Vth range (0~3V). These are very ideal to meet the IF circuit requirements. Circuit and network simulations indicate that the gate-controlled thyristor (GCT) device for the IF circuit can realize high accuracy and performance for image recognition SNN. Our novel SNN architecture with the GCT device can provide good energy efficiency (equivalent to 181TOPS/W for accumulation operations), good error tolerance to Vth variations (~10% range), and substantially smaller circuit area than that using conventional CMOS devices for IF circuit.
{"title":"A Novel Super-Steep Slope (~0.015mV/dec) Gate-Controlled Thyristor (GCT) Functional Memory Device to Support the Integrate-and-Fire Circuit for Spiking Neural Networks","authors":"Cheng-Lin Sung, H. Lue, M. Wei, S. Ho, Han-Wen Hu, P. Du, Wei-Chen Chen, C. Lo, T. Yeh, Keh-Chung Wang, Chih-Yuan Lu","doi":"10.1109/IEDM13553.2020.9372094","DOIUrl":"https://doi.org/10.1109/IEDM13553.2020.9372094","url":null,"abstract":"The analog neuromorphic circuits with functional memory devices are considered as an ultimate ideal approach to mimic the human brain for artificial intelligence (AI). The spiking neural network (SNN) with integrate-and-fire (IF) circuit is the classic building block theoretically, but so far it is very difficult to find ideal devices to realize the SNN circuit. In this work, we propose a novel functional memory that is enabled by a novel thyristor, which features super-steep slope (S.S.~0.015mV/dec), large ON/OFF ratio (> 5 orders), and tunable Vth range (0~3V). These are very ideal to meet the IF circuit requirements. Circuit and network simulations indicate that the gate-controlled thyristor (GCT) device for the IF circuit can realize high accuracy and performance for image recognition SNN. Our novel SNN architecture with the GCT device can provide good energy efficiency (equivalent to 181TOPS/W for accumulation operations), good error tolerance to Vth variations (~10% range), and substantially smaller circuit area than that using conventional CMOS devices for IF circuit.","PeriodicalId":415186,"journal":{"name":"2020 IEEE International Electron Devices Meeting (IEDM)","volume":"422 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116690095","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-12DOI: 10.1109/IEDM13553.2020.9371960
W. Banerjee, I. Karpov, A. Agrawal, S. Kim, Seungwoo Lee, Sangmin Lee, Donghwa Lee, H. Hwang
We demonstrate driving parameters to control the hybrid-filament (HF) in Ag-based threshold switching (TS) devices. To achieve statistically improved TS behavior, we engineer the nucleation energy barrier, shape of HF and steric repulsion force during TS-operation. Finally, we demonstrate TS with extremely low OFF current (0.1 pA), extremely high selectivity (> 109) with stable threshold voltage (< 3% fluctuation), high endurance (> 109) with stable steep subthreshold slope ~ 1 mV/dec, and high device-yield in Ag based devices.
{"title":"Highly-stable (< 3% fluctuation) Ag-based Threshold Switch with Extreme-low OFF Current of 0.1 pA, Extreme-high Selectivity of 109 and High Endurance of 109 Cycles","authors":"W. Banerjee, I. Karpov, A. Agrawal, S. Kim, Seungwoo Lee, Sangmin Lee, Donghwa Lee, H. Hwang","doi":"10.1109/IEDM13553.2020.9371960","DOIUrl":"https://doi.org/10.1109/IEDM13553.2020.9371960","url":null,"abstract":"We demonstrate driving parameters to control the hybrid-filament (HF) in Ag-based threshold switching (TS) devices. To achieve statistically improved TS behavior, we engineer the nucleation energy barrier, shape of HF and steric repulsion force during TS-operation. Finally, we demonstrate TS with extremely low OFF current (0.1 pA), extremely high selectivity (> 109) with stable threshold voltage (< 3% fluctuation), high endurance (> 109) with stable steep subthreshold slope ~ 1 mV/dec, and high device-yield in Ag based devices.","PeriodicalId":415186,"journal":{"name":"2020 IEEE International Electron Devices Meeting (IEDM)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124896775","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-12DOI: 10.1109/IEDM13553.2020.9371910
Yingming Lu, Xi Li, Longhao Yan, Teng Zhang, Yuchao Yang, Zhitang Song, Ru Huang
On-chip local training is highly desirable for the application of deep neural networks in environment-adaptive edge platforms, which however is hindered by the high time and energy costs of training. Here, we demonstrate efficient training of VGG-16 and LeNet-5 by optimized direct feedback alignment that replaces the layer-by-layer back propagation (BP) of errors. For the first time, the inherent stochasticity in phase change memory fabricated in 40 nm node is exploited to build a merged random feedback matrix with reduced hardware cost. Due to the physical generation of merged matrix and in-memory error computing as well as proposed conductance drift (CD) compensation protocols, the training time and energy consumptions of VGG-16 are reduced by 3× and 3.3×, respectively, compared with hardware-accelerated in-memory BP training, with 90% accuracy on CIFAR-10.
{"title":"Accelerated Local Training of CNNs by Optimized Direct Feedback Alignment Based on Stochasticity of 4 Mb C-doped Ge2Sb2Te5 PCM Chip in 40 nm Node","authors":"Yingming Lu, Xi Li, Longhao Yan, Teng Zhang, Yuchao Yang, Zhitang Song, Ru Huang","doi":"10.1109/IEDM13553.2020.9371910","DOIUrl":"https://doi.org/10.1109/IEDM13553.2020.9371910","url":null,"abstract":"On-chip local training is highly desirable for the application of deep neural networks in environment-adaptive edge platforms, which however is hindered by the high time and energy costs of training. Here, we demonstrate efficient training of VGG-16 and LeNet-5 by optimized direct feedback alignment that replaces the layer-by-layer back propagation (BP) of errors. For the first time, the inherent stochasticity in phase change memory fabricated in 40 nm node is exploited to build a merged random feedback matrix with reduced hardware cost. Due to the physical generation of merged matrix and in-memory error computing as well as proposed conductance drift (CD) compensation protocols, the training time and energy consumptions of VGG-16 are reduced by 3× and 3.3×, respectively, compared with hardware-accelerated in-memory BP training, with 90% accuracy on CIFAR-10.","PeriodicalId":415186,"journal":{"name":"2020 IEEE International Electron Devices Meeting (IEDM)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125693717","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-12DOI: 10.1109/IEDM13553.2020.9372069
K. J. Chen, Jin Wei, Gaofei Tang, Han Xu, Zheyang Zheng, Li Zhang, Wenjie Song
GaN power IC’s are expected to help unlock the full potential of GaN power electronics, especially in terms of promoting the high-frequency power switching applications. This paper first discusses a GaN power integration technology platform based on commercially available p-GaN gate HEMT technology. An integrated gate driver is presented as an example of GaN power IC with enhanced performance, in which a bootstrap unit is adopted to realize rail-to-rail output voltage and fast switching speed. To deal with GaN-specific design issues such as the unique dynamic VTH, a SPICE model of p-GaN gate HEMT is developed to improve design accuracy. Future prospects for GaN power integration are discussed by extending the integration’s landscape to multi-functional GaN power devices, GaN CMOS technology, and GaN/SiC hybrid power IC’s.
{"title":"Planar GaN Power Integration – The World is Flat","authors":"K. J. Chen, Jin Wei, Gaofei Tang, Han Xu, Zheyang Zheng, Li Zhang, Wenjie Song","doi":"10.1109/IEDM13553.2020.9372069","DOIUrl":"https://doi.org/10.1109/IEDM13553.2020.9372069","url":null,"abstract":"GaN power IC’s are expected to help unlock the full potential of GaN power electronics, especially in terms of promoting the high-frequency power switching applications. This paper first discusses a GaN power integration technology platform based on commercially available p-GaN gate HEMT technology. An integrated gate driver is presented as an example of GaN power IC with enhanced performance, in which a bootstrap unit is adopted to realize rail-to-rail output voltage and fast switching speed. To deal with GaN-specific design issues such as the unique dynamic VTH, a SPICE model of p-GaN gate HEMT is developed to improve design accuracy. Future prospects for GaN power integration are discussed by extending the integration’s landscape to multi-functional GaN power devices, GaN CMOS technology, and GaN/SiC hybrid power IC’s.","PeriodicalId":415186,"journal":{"name":"2020 IEEE International Electron Devices Meeting (IEDM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116447070","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-12DOI: 10.1109/IEDM13553.2020.9372031
J. Grahn, E. Cha, A. Pourkabirian, J. Stenarson, N. Wadefalk
The InP HEMT is the preferred transistor technology for cryogenic low-noise amplification from 1 GHz up to 200 GHz. The InP HEMT shows its superiority at temperatures 5 to 15 K and technology development must be made with knowledge about the special circumstances occurring in III- V materials and device operating under cryogenic conditions. We report on how to electrically stabilize the cryogenic two-finger HEMT at low temperature making it possible to design low-noise amplifiers with state of the art noise performance up to mm-wave. We also demonstrate recent progress on optimizing the InP HEMT for cryogenic low-noise amplifier operation below 1 mW dc power dissipation, of interest for qubit readout electronics.
{"title":"III-V HEMTs for Cryogenic Low Noise Amplifiers","authors":"J. Grahn, E. Cha, A. Pourkabirian, J. Stenarson, N. Wadefalk","doi":"10.1109/IEDM13553.2020.9372031","DOIUrl":"https://doi.org/10.1109/IEDM13553.2020.9372031","url":null,"abstract":"The InP HEMT is the preferred transistor technology for cryogenic low-noise amplification from 1 GHz up to 200 GHz. The InP HEMT shows its superiority at temperatures 5 to 15 K and technology development must be made with knowledge about the special circumstances occurring in III- V materials and device operating under cryogenic conditions. We report on how to electrically stabilize the cryogenic two-finger HEMT at low temperature making it possible to design low-noise amplifiers with state of the art noise performance up to mm-wave. We also demonstrate recent progress on optimizing the InP HEMT for cryogenic low-noise amplifier operation below 1 mW dc power dissipation, of interest for qubit readout electronics.","PeriodicalId":415186,"journal":{"name":"2020 IEEE International Electron Devices Meeting (IEDM)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116518965","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-12DOI: 10.1109/IEDM13553.2020.9372045
K. Okada
In this presentation, a 28-GHz phased-array transceiver and 300GHz transceiver realized by 65nm CMOS will be introduced, which are designed for 5G and beyond. The talk concludes with a discussion on future directions of millimeter-wave wireless communication, based on Shannon and Friis equations.
{"title":"Millimeter-Wave CMOS Phased-Array Transceiver for 5G and Beyond","authors":"K. Okada","doi":"10.1109/IEDM13553.2020.9372045","DOIUrl":"https://doi.org/10.1109/IEDM13553.2020.9372045","url":null,"abstract":"In this presentation, a 28-GHz phased-array transceiver and 300GHz transceiver realized by 65nm CMOS will be introduced, which are designed for 5G and beyond. The talk concludes with a discussion on future directions of millimeter-wave wireless communication, based on Shannon and Friis equations.","PeriodicalId":415186,"journal":{"name":"2020 IEEE International Electron Devices Meeting (IEDM)","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122681489","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-12DOI: 10.1109/IEDM13553.2020.9371954
P. Chevalier, F. Gianesello, A. Pallotta, J. A. Gonçalves, G. Bertrand, J. Borrel, L. Boissonnet, E. Brezza, M. Buczko, E. Canderle, D. Céli, S. Crémer, N. Derrier, C. Diouf, C. Durand, F. Foussadier, P. Garcia, N. Guitard, A. Fleury, A. Gauthier, O. Kermarrec, J. Lajoinie, C. Legrand, V. Milon, F. Monsieur, Y. Mourier, D. Muller, D. Ney, R. Paulin, N. Pelloux, C. Renard, M. Rellier, P. Scheer, I. Sicard, N. Vulliet, A. Juge, E. Granger, D. Gloria, J. Uginet, L. Garchery, F. Paillardet
While 5G wireless networks are currently deployed around the world, preliminary research activities have begun to look beyond 5G and conceptualize 6G standard. Although it is envisioned that 6G may bring an unprecedent transformation of the wireless networks in comparison with previous generations, the necessity to develop analog and RF specialized technologies to address new frequency spectra will remain. In this paper, we review the development of PD-SOI CMOS and SiGe BiCMOS technologies addressing 5G RF Integrated Circuits (RFICs) and their evolutions for 6G.
{"title":"PD-SOI CMOS and SiGe BiCMOS Technologies for 5G and 6G communications","authors":"P. Chevalier, F. Gianesello, A. Pallotta, J. A. Gonçalves, G. Bertrand, J. Borrel, L. Boissonnet, E. Brezza, M. Buczko, E. Canderle, D. Céli, S. Crémer, N. Derrier, C. Diouf, C. Durand, F. Foussadier, P. Garcia, N. Guitard, A. Fleury, A. Gauthier, O. Kermarrec, J. Lajoinie, C. Legrand, V. Milon, F. Monsieur, Y. Mourier, D. Muller, D. Ney, R. Paulin, N. Pelloux, C. Renard, M. Rellier, P. Scheer, I. Sicard, N. Vulliet, A. Juge, E. Granger, D. Gloria, J. Uginet, L. Garchery, F. Paillardet","doi":"10.1109/IEDM13553.2020.9371954","DOIUrl":"https://doi.org/10.1109/IEDM13553.2020.9371954","url":null,"abstract":"While 5G wireless networks are currently deployed around the world, preliminary research activities have begun to look beyond 5G and conceptualize 6G standard. Although it is envisioned that 6G may bring an unprecedent transformation of the wireless networks in comparison with previous generations, the necessity to develop analog and RF specialized technologies to address new frequency spectra will remain. In this paper, we review the development of PD-SOI CMOS and SiGe BiCMOS technologies addressing 5G RF Integrated Circuits (RFICs) and their evolutions for 6G.","PeriodicalId":415186,"journal":{"name":"2020 IEEE International Electron Devices Meeting (IEDM)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117075048","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-12DOI: 10.1109/IEDM13553.2020.9372101
H. Lue, Guan-Ru Lee, T. Yeh, T. Hsu, C. Lo, Cheng-Lin Sung, Wei-Chen Chen, Chiatze Huang, Kuan-Yuan Shen, Meng-Yen Wu, Pishan Tseng, Min-Feng Hung, C. Chiu, K. Hsieh, Keh-Chung Wang, Chih-Yuan Lu
We demonstrate a 3D stackable AND-type Flash memory architecture for high-density and fast-read non-volatile memory solution. The device is based on a gate-all-around (GAA) macaroni thin-body device, with two vertical buried diffusion lines by N+ doped poly plug to connect all memory cells in a parallel way to achieve 3D AND-type array. High sensing current >6uA enables fast Tread ~100ns like NOR Flash, while the structure can enable hundreds of stacked layers eventually. Large transistor ON/OFF ratio of >5 orders, >5V Vt memory window, 100K Endurance, read-disturb free property, and small RTN are demonstrated in our 3D architecture using the BE-MANOS charge-trapping device. This architecture is promising to realize high-density 3D NOR Flash and future storage-class memory (SCM).
{"title":"3D AND: A 3D Stackable Flash Memory Architecture to Realize High-Density and Fast-Read 3D NOR Flash and Storage-Class Memory","authors":"H. Lue, Guan-Ru Lee, T. Yeh, T. Hsu, C. Lo, Cheng-Lin Sung, Wei-Chen Chen, Chiatze Huang, Kuan-Yuan Shen, Meng-Yen Wu, Pishan Tseng, Min-Feng Hung, C. Chiu, K. Hsieh, Keh-Chung Wang, Chih-Yuan Lu","doi":"10.1109/IEDM13553.2020.9372101","DOIUrl":"https://doi.org/10.1109/IEDM13553.2020.9372101","url":null,"abstract":"We demonstrate a 3D stackable AND-type Flash memory architecture for high-density and fast-read non-volatile memory solution. The device is based on a gate-all-around (GAA) macaroni thin-body device, with two vertical buried diffusion lines by N+ doped poly plug to connect all memory cells in a parallel way to achieve 3D AND-type array. High sensing current >6uA enables fast Tread ~100ns like NOR Flash, while the structure can enable hundreds of stacked layers eventually. Large transistor ON/OFF ratio of >5 orders, >5V Vt memory window, 100K Endurance, read-disturb free property, and small RTN are demonstrated in our 3D architecture using the BE-MANOS charge-trapping device. This architecture is promising to realize high-density 3D NOR Flash and future storage-class memory (SCM).","PeriodicalId":415186,"journal":{"name":"2020 IEEE International Electron Devices Meeting (IEDM)","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124725395","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-12DOI: 10.1109/IEDM13553.2020.9372102
Hoonhee Han, R. Choi, Seong-ook Jung, S. Chung, B. Cho, S. C. Song, C. Choi
We demonstrated low temperature (< 500 °C) and hydrogen ion-cut based monolithic 3D (M3D) process integration platform with CMOS circuits, memory devices and photo-sensitive sensors. Top Si layer was transferred on the 8-inch bottom Si substrate having standard CMOS circuits using hydrogen ion implantation, bonding and cleavage under low thermal annealing. Ta2O5-RRAM and a-IGZO photo detector devices on the upper transferred Si layer were vertically stacked with CMOS circuits. Bonding and top Si layer transfer are considerably affected by ion implantation process, ILD, surface treatment, oxide CMP and annealing. Different light intensity to photodetector at the upper layer modulates the frequency of current sensor with 21 stage ring- oscillator at the lower layer and current level in RRAM at the upper layer is also modulated by input frequency from CMOS devices. The functionalities of ion-cut based M3D integration platform are confirmed by higher frequency and current level with respect to light intensity.
{"title":"Low Temperature and Ion-Cut Based Monolithic 3D Process Integration Platform Incorporated with CMOS, RRAM and Photo-Sensor Circuits","authors":"Hoonhee Han, R. Choi, Seong-ook Jung, S. Chung, B. Cho, S. C. Song, C. Choi","doi":"10.1109/IEDM13553.2020.9372102","DOIUrl":"https://doi.org/10.1109/IEDM13553.2020.9372102","url":null,"abstract":"We demonstrated low temperature (< 500 °C) and hydrogen ion-cut based monolithic 3D (M3D) process integration platform with CMOS circuits, memory devices and photo-sensitive sensors. Top Si layer was transferred on the 8-inch bottom Si substrate having standard CMOS circuits using hydrogen ion implantation, bonding and cleavage under low thermal annealing. Ta2O5-RRAM and a-IGZO photo detector devices on the upper transferred Si layer were vertically stacked with CMOS circuits. Bonding and top Si layer transfer are considerably affected by ion implantation process, ILD, surface treatment, oxide CMP and annealing. Different light intensity to photodetector at the upper layer modulates the frequency of current sensor with 21 stage ring- oscillator at the lower layer and current level in RRAM at the upper layer is also modulated by input frequency from CMOS devices. The functionalities of ion-cut based M3D integration platform are confirmed by higher frequency and current level with respect to light intensity.","PeriodicalId":415186,"journal":{"name":"2020 IEEE International Electron Devices Meeting (IEDM)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128066937","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-12DOI: 10.1109/iedm13553.2020.9372100
K. Saraswat
While dimension scaling, introduction of new materials and novel device structures has enhanced the transistor performance, the opposite is true for the interconnects. Looking into the future the relentless scaling paradigm is threatened by the limits of copper/low-k interconnects. Thus, it is imperative to examine alternate interconnect schemes and explore possible advantages of novel potential candidates. Optical interconnects and three-dimensional (3-D) heterogeneous integration have emerged as potential candidates to mitigate the interconnect tyranny by providing lower power dissipation, improved communication bandwidth, and signal latency. This talk will focus on the most important devices and technologies for integration of these on the silicon platform.
{"title":"Silicon compatible optical interconnect and monolithic 3-D integration","authors":"K. Saraswat","doi":"10.1109/iedm13553.2020.9372100","DOIUrl":"https://doi.org/10.1109/iedm13553.2020.9372100","url":null,"abstract":"While dimension scaling, introduction of new materials and novel device structures has enhanced the transistor performance, the opposite is true for the interconnects. Looking into the future the relentless scaling paradigm is threatened by the limits of copper/low-k interconnects. Thus, it is imperative to examine alternate interconnect schemes and explore possible advantages of novel potential candidates. Optical interconnects and three-dimensional (3-D) heterogeneous integration have emerged as potential candidates to mitigate the interconnect tyranny by providing lower power dissipation, improved communication bandwidth, and signal latency. This talk will focus on the most important devices and technologies for integration of these on the silicon platform.","PeriodicalId":415186,"journal":{"name":"2020 IEEE International Electron Devices Meeting (IEDM)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127983205","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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