Reliability of copper dual damascene influenced by pre-clean

Abstract

Copper damascene processing was introduced to reduce circuit speed limiting interconnect RC delays. To prevent copper diffusion into the neighboring dielectric, copper is encapsulated into metallic and dielectric barriers. On the dual damascene level, prior to copper metallization, a pre-clean is applied in order to clean via bottoms. This is necessary to improve yield and decrease via resistance. Conventional preclean employs directional Ar+ bombardment of the wafer surface. This leads to facetting of recess openings and copper sputtering from the underlying metal layer, which is then re-deposited onto recess bottoms. Although several papers detail the impact of pre-clean on via resistance none of them treats in detail the eventual issues related to copper re-deposition underneath the metallic barrier in direct contact with the dielectric. The present paper shows how conventional pre-clean can influence Cu+ drift rate due to copper re-deposition, plasma damage and via resistance.