Pub Date : 2002-11-07DOI: 10.1109/IPFA.2002.1025668
S. K. Manhas, M. M. De Souza, A. Oates, Y. Chen
The effect of oxide damage on the electron mobility in n-channel inversion layers is studied. It is observed that as a result of stress, the universal mobility model becomes interface charge dependent. The effect of interface damage, attributed to Coulomb scattering in the region of strong inversion, can be described by a change in universal model parameters with interface charge (N/sub it/). An N/sub it/-dependent model is presented which can be easily assimilated in simulation tools by circuit designers to accurately predict impact of device degradation on performance.
{"title":"Impact of oxide degradation on universal mobility behaviour of n-MOS inversion layers","authors":"S. K. Manhas, M. M. De Souza, A. Oates, Y. Chen","doi":"10.1109/IPFA.2002.1025668","DOIUrl":"https://doi.org/10.1109/IPFA.2002.1025668","url":null,"abstract":"The effect of oxide damage on the electron mobility in n-channel inversion layers is studied. It is observed that as a result of stress, the universal mobility model becomes interface charge dependent. The effect of interface damage, attributed to Coulomb scattering in the region of strong inversion, can be described by a change in universal model parameters with interface charge (N/sub it/). An N/sub it/-dependent model is presented which can be easily assimilated in simulation tools by circuit designers to accurately predict impact of device degradation on performance.","PeriodicalId":328714,"journal":{"name":"Proceedings of the 9th International Symposium on the Physical and Failure Analysis of Integrated Circuits (Cat. No.02TH8614)","volume":"302 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114387202","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-11-07DOI: 10.1109/IPFA.2002.1025602
J. Yue, D. Su, Y. W. Yau, K. L. Young, T. W. Goh
Pure-play integrated circuits (IC) foundries, companies whose business is exclusively to manufacture ICs for other companies, have been in existence for about 15 years now, and have been one of the success stories of the semiconductor industry. Over this period of time, foundries have transformed from technology-trailing companies into technology-leading manufacturers. Many changes occurred to make this happen. As the dedicated. foundry concept matures, new challenges arise that will require further transformations. In particular, this article focuses on the changes in the role of the quality and reliability (QR) organization in foundries, and the driving forces that will signify more future changes.
{"title":"The changing role and future challenges of quality and reliability in the foundry industry","authors":"J. Yue, D. Su, Y. W. Yau, K. L. Young, T. W. Goh","doi":"10.1109/IPFA.2002.1025602","DOIUrl":"https://doi.org/10.1109/IPFA.2002.1025602","url":null,"abstract":"Pure-play integrated circuits (IC) foundries, companies whose business is exclusively to manufacture ICs for other companies, have been in existence for about 15 years now, and have been one of the success stories of the semiconductor industry. Over this period of time, foundries have transformed from technology-trailing companies into technology-leading manufacturers. Many changes occurred to make this happen. As the dedicated. foundry concept matures, new challenges arise that will require further transformations. In particular, this article focuses on the changes in the role of the quality and reliability (QR) organization in foundries, and the driving forces that will signify more future changes.","PeriodicalId":328714,"journal":{"name":"Proceedings of the 9th International Symposium on the Physical and Failure Analysis of Integrated Circuits (Cat. No.02TH8614)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121695424","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-11-07DOI: 10.1109/IPFA.2002.1025606
N. Mohapatra, S. Mahapatra, V. Rao
This paper analyzes in detail the damage generation in n-channel MOS transistors operating in the substrate enhanced gate current (SEGC) regime. The results are also compared with the damage generated during conventional hot carrier stress experiments. Stressing and charge pumping experiments are carried out to study the degradation with different substrate bias. Our results clearly show that the application of a substrate bias enhances degradation, which is strongly dependent on the transverse electric field and spread of the interface trap profile. The possible mechanisms responsible for such trends are discussed.
{"title":"The study of damage generation in n-channel MOS transistors operating in the substrate enhanced gate current regime","authors":"N. Mohapatra, S. Mahapatra, V. Rao","doi":"10.1109/IPFA.2002.1025606","DOIUrl":"https://doi.org/10.1109/IPFA.2002.1025606","url":null,"abstract":"This paper analyzes in detail the damage generation in n-channel MOS transistors operating in the substrate enhanced gate current (SEGC) regime. The results are also compared with the damage generated during conventional hot carrier stress experiments. Stressing and charge pumping experiments are carried out to study the degradation with different substrate bias. Our results clearly show that the application of a substrate bias enhances degradation, which is strongly dependent on the transverse electric field and spread of the interface trap profile. The possible mechanisms responsible for such trends are discussed.","PeriodicalId":328714,"journal":{"name":"Proceedings of the 9th International Symposium on the Physical and Failure Analysis of Integrated Circuits (Cat. No.02TH8614)","volume":"110 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124687928","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-11-07DOI: 10.1109/IPFA.2002.1025639
K. Li, F. Yan, E. Er, S. Redkar
With integrated circuits going into the 0.18 /spl mu/m generation and below, transmission electron microscopy (TEM) is becoming more routinely used and indispensable for equipment qualification, process monitoring and optimization, technology development, and failure analysis. However, TEM analysis is required to be more sample thickness forgivable. Scanning transmission electron microscopy (STEM) is a very good candidate for these purposes, as STEM can handle thicker TEM samples. By varying the camera length, the scattered angle of electrons forming STEM images changes. At large scattering angles, the scattering cross section is strongly atomic number (Z) dependent (D.B. Williams and C.B. Carter, Transmission Electron Microscopy, Plenum Press, New York and London, p. 41, 1996). Therefore the image contrast is dominated by Z and Z-contrast imaging is thus named. In this paper, we utilize the Z-contrast imaging technique to study the influence of different pre-copper/tantalum deposition cleaning scheme on the formation of Cu dual damascene structure of 0.13 /spl mu/m technology node. The results clearly show that Z-contrast STEM imaging can be applied successfully to overcome some of the difficulties encountered in normal TEM observations, and it is a very useful tool for process optimization.
{"title":"Application of Z-contrast imaging in deep-sub-micron process optimization","authors":"K. Li, F. Yan, E. Er, S. Redkar","doi":"10.1109/IPFA.2002.1025639","DOIUrl":"https://doi.org/10.1109/IPFA.2002.1025639","url":null,"abstract":"With integrated circuits going into the 0.18 /spl mu/m generation and below, transmission electron microscopy (TEM) is becoming more routinely used and indispensable for equipment qualification, process monitoring and optimization, technology development, and failure analysis. However, TEM analysis is required to be more sample thickness forgivable. Scanning transmission electron microscopy (STEM) is a very good candidate for these purposes, as STEM can handle thicker TEM samples. By varying the camera length, the scattered angle of electrons forming STEM images changes. At large scattering angles, the scattering cross section is strongly atomic number (Z) dependent (D.B. Williams and C.B. Carter, Transmission Electron Microscopy, Plenum Press, New York and London, p. 41, 1996). Therefore the image contrast is dominated by Z and Z-contrast imaging is thus named. In this paper, we utilize the Z-contrast imaging technique to study the influence of different pre-copper/tantalum deposition cleaning scheme on the formation of Cu dual damascene structure of 0.13 /spl mu/m technology node. The results clearly show that Z-contrast STEM imaging can be applied successfully to overcome some of the difficulties encountered in normal TEM observations, and it is a very useful tool for process optimization.","PeriodicalId":328714,"journal":{"name":"Proceedings of the 9th International Symposium on the Physical and Failure Analysis of Integrated Circuits (Cat. No.02TH8614)","volume":"05 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130656419","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-11-07DOI: 10.1109/IPFA.2002.1025622
V.K. Wong, C.H. Lock, K. H. Siek, P. J. Tan
A simple defect localization scheme for 6 transistor SRAM cells was presented. Parametric measurements for all transistors forming the pull ups and pull downs enable the understanding of the change in feedback behaviour of the memory cell, leading to failure models and defect behaviour. This technique leads to an intuitive and time efficient method to identify failing areas in the memory cell. It underscores the importance of circuit analysis before embarking on physical failure analysis to reduce the area for physical analysis and increase chances of finding the actual defect.
{"title":"Electrical analysis to fault isolate defects in 6T memory cells","authors":"V.K. Wong, C.H. Lock, K. H. Siek, P. J. Tan","doi":"10.1109/IPFA.2002.1025622","DOIUrl":"https://doi.org/10.1109/IPFA.2002.1025622","url":null,"abstract":"A simple defect localization scheme for 6 transistor SRAM cells was presented. Parametric measurements for all transistors forming the pull ups and pull downs enable the understanding of the change in feedback behaviour of the memory cell, leading to failure models and defect behaviour. This technique leads to an intuitive and time efficient method to identify failing areas in the memory cell. It underscores the importance of circuit analysis before embarking on physical failure analysis to reduce the area for physical analysis and increase chances of finding the actual defect.","PeriodicalId":328714,"journal":{"name":"Proceedings of the 9th International Symposium on the Physical and Failure Analysis of Integrated Circuits (Cat. No.02TH8614)","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127877180","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-11-07DOI: 10.1109/IPFA.2002.1025610
Lam Tim Fai
FEA contact element technique has been established and was successfully applied to metal lead forming simulation. One of the commonly encountered lead finish defects, the lead shift problem, was studied in more detail. The results clearly show that the lead shift is due to the unsymmetrical profile of the lead frame used. The FEA results are in good accordance with the experimental measurement.
{"title":"FEA contact element technique and its applications in metal lead forming failure analysis","authors":"Lam Tim Fai","doi":"10.1109/IPFA.2002.1025610","DOIUrl":"https://doi.org/10.1109/IPFA.2002.1025610","url":null,"abstract":"FEA contact element technique has been established and was successfully applied to metal lead forming simulation. One of the commonly encountered lead finish defects, the lead shift problem, was studied in more detail. The results clearly show that the lead shift is due to the unsymmetrical profile of the lead frame used. The FEA results are in good accordance with the experimental measurement.","PeriodicalId":328714,"journal":{"name":"Proceedings of the 9th International Symposium on the Physical and Failure Analysis of Integrated Circuits (Cat. No.02TH8614)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116645075","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-11-07DOI: 10.1109/IPFA.2002.1025672
W. Loh, B. Cho
In ultra-thin (20 /spl Aring/) gate oxide, it is observed that gate leakage current increases in discrete steps similar to quasi-breakdown in thicker oxide. A direct correlation is observed between this gate leakage and interface traps when stressed under both positive and negative gate polarity. Using different sample area, it is observed that this gate leakage current is highly localized but has a weak area dependency.
{"title":"Correlation between interface traps and gate leakage current in ultrathin silicon dioxides","authors":"W. Loh, B. Cho","doi":"10.1109/IPFA.2002.1025672","DOIUrl":"https://doi.org/10.1109/IPFA.2002.1025672","url":null,"abstract":"In ultra-thin (20 /spl Aring/) gate oxide, it is observed that gate leakage current increases in discrete steps similar to quasi-breakdown in thicker oxide. A direct correlation is observed between this gate leakage and interface traps when stressed under both positive and negative gate polarity. Using different sample area, it is observed that this gate leakage current is highly localized but has a weak area dependency.","PeriodicalId":328714,"journal":{"name":"Proceedings of the 9th International Symposium on the Physical and Failure Analysis of Integrated Circuits (Cat. No.02TH8614)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122511424","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-11-07DOI: 10.1109/IPFA.2002.1025607
J.F. Chen, C. Tsao
Hot-carrier induced drain current degradation in 0.18 /spl mu/m nMOSFETs is investigated. Results show that drain current characterized at drain voltage higher than 0.1 V exhibits the most degradation. This new observation is attributed to two competing mechanisms as the characterization drain voltage increases: reduction in channel inversion charges, and reduction in charged interface states. The characteristic of drain current degradation vs. characterization drain voltage is flatter when the device is stressed under high temperature and forward body-bias.
{"title":"A new observation in hot-carrier induced drain current degradation in deep-sub-micrometer nMOSFETs","authors":"J.F. Chen, C. Tsao","doi":"10.1109/IPFA.2002.1025607","DOIUrl":"https://doi.org/10.1109/IPFA.2002.1025607","url":null,"abstract":"Hot-carrier induced drain current degradation in 0.18 /spl mu/m nMOSFETs is investigated. Results show that drain current characterized at drain voltage higher than 0.1 V exhibits the most degradation. This new observation is attributed to two competing mechanisms as the characterization drain voltage increases: reduction in channel inversion charges, and reduction in charged interface states. The characteristic of drain current degradation vs. characterization drain voltage is flatter when the device is stressed under high temperature and forward body-bias.","PeriodicalId":328714,"journal":{"name":"Proceedings of the 9th International Symposium on the Physical and Failure Analysis of Integrated Circuits (Cat. No.02TH8614)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130191142","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-11-07DOI: 10.1109/IPFA.2002.1025673
Y.M. Mutha, R. Lal, V. Ramgopal Rao
An experimental study of the dielectric degradation under different AC stress conditions has been carried out using MOSFETs with 3.9 nm thick gate oxides. Bipolar and unipolar voltage pulses were used to stress the dielectric and interface state generation monitored. Pulse parameters (pulse levels, duty cycle, stress time, rise/fall times, and frequency) were systematically varied to understand the processes responsible for degradation. The experimental results give a good insight into the physical mechanisms responsible for interface degradation in ultra-thin gate oxides. The observations can be explained invoking carrier injection into the oxide followed by trapped-hole recombination.
{"title":"Physical mechanisms for pulsed AC stress degradation in thin gate oxide MOSFETs","authors":"Y.M. Mutha, R. Lal, V. Ramgopal Rao","doi":"10.1109/IPFA.2002.1025673","DOIUrl":"https://doi.org/10.1109/IPFA.2002.1025673","url":null,"abstract":"An experimental study of the dielectric degradation under different AC stress conditions has been carried out using MOSFETs with 3.9 nm thick gate oxides. Bipolar and unipolar voltage pulses were used to stress the dielectric and interface state generation monitored. Pulse parameters (pulse levels, duty cycle, stress time, rise/fall times, and frequency) were systematically varied to understand the processes responsible for degradation. The experimental results give a good insight into the physical mechanisms responsible for interface degradation in ultra-thin gate oxides. The observations can be explained invoking carrier injection into the oxide followed by trapped-hole recombination.","PeriodicalId":328714,"journal":{"name":"Proceedings of the 9th International Symposium on the Physical and Failure Analysis of Integrated Circuits (Cat. No.02TH8614)","volume":"331 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134152003","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-11-07DOI: 10.1109/IPFA.2002.1025603
C. Boit
This paper is an approach to establish a complete business model for failure analysis (FA) as a high tech service provider in the world of microelectronics, from the introduction of analysis process flows, over correlation of equipment/skills with the technologies and products that the lab is supporting, to a key performance indicators (KPI)-based operation that handles the interdependencies of workload and cycle time and opens the path to quantitative target setting agreements with the customer's inclusive introduction into balanced score card controlling. A complete system, built upon all the presented parts, leads to a database that can calculate all the parameters for an FA lab from scratch, tailored exactly to the demand of the customer. Such a database acts as reference lab and defines best FA practice.
{"title":"Failure analysis tailored to demand a business model for high tech service","authors":"C. Boit","doi":"10.1109/IPFA.2002.1025603","DOIUrl":"https://doi.org/10.1109/IPFA.2002.1025603","url":null,"abstract":"This paper is an approach to establish a complete business model for failure analysis (FA) as a high tech service provider in the world of microelectronics, from the introduction of analysis process flows, over correlation of equipment/skills with the technologies and products that the lab is supporting, to a key performance indicators (KPI)-based operation that handles the interdependencies of workload and cycle time and opens the path to quantitative target setting agreements with the customer's inclusive introduction into balanced score card controlling. A complete system, built upon all the presented parts, leads to a database that can calculate all the parameters for an FA lab from scratch, tailored exactly to the demand of the customer. Such a database acts as reference lab and defines best FA practice.","PeriodicalId":328714,"journal":{"name":"Proceedings of the 9th International Symposium on the Physical and Failure Analysis of Integrated Circuits (Cat. No.02TH8614)","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125056349","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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