{"title":"A compact analytical current model including traps effects for GS DG MOSFETs","authors":"T. Bentercia, F. Djeffal, M. Abdi, D. Arar","doi":"10.1109/SM2ACD.2010.5672338","DOIUrl":null,"url":null,"abstract":"Due to the excellent control of DG MOSFETs over the short channel effects, they have been considered as a leading candidate to extend the scaling limit of conventional bulk MOSFETs. However, the hot carrier injection into gate oxides remains a potential problem in reliability field hence altering the device lifetime. In the present paper, a comprehensive drain current model incorporating hot-carrier-induced degradation effect is developed, the derivation is carried out based on some assumptions regarding threshold voltage and mobility. Using obtained model, we have studied the utility of adding a high-k layer into the device structure for which an improvement is detected, the accuracy and efficiency make our analytic current-voltage model for DG MOSFETs suitable for circuit simulation programs.","PeriodicalId":442381,"journal":{"name":"2010 XIth International Workshop on Symbolic and Numerical Methods, Modeling and Applications to Circuit Design (SM2ACD)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 XIth International Workshop on Symbolic and Numerical Methods, Modeling and Applications to Circuit Design (SM2ACD)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SM2ACD.2010.5672338","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
Due to the excellent control of DG MOSFETs over the short channel effects, they have been considered as a leading candidate to extend the scaling limit of conventional bulk MOSFETs. However, the hot carrier injection into gate oxides remains a potential problem in reliability field hence altering the device lifetime. In the present paper, a comprehensive drain current model incorporating hot-carrier-induced degradation effect is developed, the derivation is carried out based on some assumptions regarding threshold voltage and mobility. Using obtained model, we have studied the utility of adding a high-k layer into the device structure for which an improvement is detected, the accuracy and efficiency make our analytic current-voltage model for DG MOSFETs suitable for circuit simulation programs.
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