Pub Date : 2010-12-17DOI: 10.1109/SM2ACD.2010.5672321
N. Lakhdar, F. Djeffal, M. Abdi, D. Arar
In this work, a deep submicron double-gate (DG) Gallium Nitride (GaN)-MESFET design and its 2-D threshold analytical model have been proposed and expected to suppress the short-channel-effects for deep submicron GaN-MESFET-based low power applications. The model predicts that the threshold voltage is greatly improved in comparison with the conventional Single-Gate GaN-MESFET. The developed approaches are verified and validated by the good agreement found with the 2D numerical simulations for wide range of device parameters and bias conditions. DG GaN-MESFET can alleviate the critical problem and further improve the immunity of short-channel-effects of GaN-MESFET-based circuits in the low power deep submicron devices.
{"title":"An analytical threshold voltage model to study the scaling capability of deep submicron double-gate GaN-MESFETs","authors":"N. Lakhdar, F. Djeffal, M. Abdi, D. Arar","doi":"10.1109/SM2ACD.2010.5672321","DOIUrl":"https://doi.org/10.1109/SM2ACD.2010.5672321","url":null,"abstract":"In this work, a deep submicron double-gate (DG) Gallium Nitride (GaN)-MESFET design and its 2-D threshold analytical model have been proposed and expected to suppress the short-channel-effects for deep submicron GaN-MESFET-based low power applications. The model predicts that the threshold voltage is greatly improved in comparison with the conventional Single-Gate GaN-MESFET. The developed approaches are verified and validated by the good agreement found with the 2D numerical simulations for wide range of device parameters and bias conditions. DG GaN-MESFET can alleviate the critical problem and further improve the immunity of short-channel-effects of GaN-MESFET-based circuits in the low power deep submicron devices.","PeriodicalId":442381,"journal":{"name":"2010 XIth International Workshop on Symbolic and Numerical Methods, Modeling and Applications to Circuit Design (SM2ACD)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126151004","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-12-17DOI: 10.1109/SM2ACD.2010.5672350
Amira Kheriji, F. Bouani, M. Ksouri
This paper proposes a new mathematical method to solve min-max predictive controller for a class of constrained linear Multi Input Multi Output (MIMO) systems. A parametric uncertainty state space model is adopted to describe the dynamic behavior of the real process. Since the resulting optimization problem is non convex, a deterministic global optimization technique is adopted to solve it which is the Generalized Geometric Programming (GGP). The key idea of this method is to transform the initial non convex optimization problem to a convex one by means of variable transformations. The main achievement is that the optimal control value found with the GGP shows successful set point tracking and constraints satisfaction. Moreover, an efficient implementation of this approach will lead to an algorithm with a low computational burden. The main features of the new algorithm are illustrated through a MIMO system.
{"title":"GGP approach to solve non convex min-max robust model predictive controller for a class of constrained MIMO systems","authors":"Amira Kheriji, F. Bouani, M. Ksouri","doi":"10.1109/SM2ACD.2010.5672350","DOIUrl":"https://doi.org/10.1109/SM2ACD.2010.5672350","url":null,"abstract":"This paper proposes a new mathematical method to solve min-max predictive controller for a class of constrained linear Multi Input Multi Output (MIMO) systems. A parametric uncertainty state space model is adopted to describe the dynamic behavior of the real process. Since the resulting optimization problem is non convex, a deterministic global optimization technique is adopted to solve it which is the Generalized Geometric Programming (GGP). The key idea of this method is to transform the initial non convex optimization problem to a convex one by means of variable transformations. The main achievement is that the optimal control value found with the GGP shows successful set point tracking and constraints satisfaction. Moreover, an efficient implementation of this approach will lead to an algorithm with a low computational burden. The main features of the new algorithm are illustrated through a MIMO system.","PeriodicalId":442381,"journal":{"name":"2010 XIth International Workshop on Symbolic and Numerical Methods, Modeling and Applications to Circuit Design (SM2ACD)","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114378821","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-12-17DOI: 10.1109/SM2ACD.2010.5672318
Toshinori Yamada
This paper presents that the degree of sequential diagnosability of an N-vertex Cayley graph is Ω(N/D) by generalizing a known technique of finding a lower bound for that of a CCC(cube-connected cycles), where D is the diameter of the Cayley graph. From the lower bound, it is shown that the degrees of sequential diagnosability of the N-vertex star graph and wrapped butterfly are Ω(N log log N/logN) and Ω(N/logN), respectively.
{"title":"Lower bound for degree of sequential diagnosability of Cayley graphs","authors":"Toshinori Yamada","doi":"10.1109/SM2ACD.2010.5672318","DOIUrl":"https://doi.org/10.1109/SM2ACD.2010.5672318","url":null,"abstract":"This paper presents that the degree of sequential diagnosability of an N-vertex Cayley graph is Ω(N/D) by generalizing a known technique of finding a lower bound for that of a CCC(cube-connected cycles), where D is the diameter of the Cayley graph. From the lower bound, it is shown that the degrees of sequential diagnosability of the N-vertex star graph and wrapped butterfly are Ω(N log log N/logN) and Ω(N/logN), respectively.","PeriodicalId":442381,"journal":{"name":"2010 XIth International Workshop on Symbolic and Numerical Methods, Modeling and Applications to Circuit Design (SM2ACD)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117240451","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-12-17DOI: 10.1109/SM2ACD.2010.5672297
C. Diab, M. Oueidat
This paper proposes a method for the design of adaptive scalar quantizer based on the source statistics. Adaptivity is useful in applications where the statistics of the source are either not known a priori or will change over time. The proposed method first determines two quantizer cells and the corresponding output levels such that the distortion is minimized over all possible two-level quantizers. Then the cell with the largest empirical distortion is split into two cells in such a way that the empirical distortion is minimized over all possible splits. Each time a split is made, the number of output levels increases by one until the target number of cells is reached. Finally, the resultant quantizer serves as a good initial starting point for running the Lloyd-Max Algorithm in order to reach global optimality. Experimental results show that this new designed quantizer outperforms that obtained by the Lloyd-Max method started with an arbitrary initial point in terms of Mean Square Error (MSE). Moreover, the proposed method converges more rapidly than the Lloyd-Max one. Our method adapts itself to the histogram of the data without creating any empty output range. This feature improves the robustness of the design method.
{"title":"A novel approach to design a robust and optimal scalar quantizer for any non-standard input density","authors":"C. Diab, M. Oueidat","doi":"10.1109/SM2ACD.2010.5672297","DOIUrl":"https://doi.org/10.1109/SM2ACD.2010.5672297","url":null,"abstract":"This paper proposes a method for the design of adaptive scalar quantizer based on the source statistics. Adaptivity is useful in applications where the statistics of the source are either not known a priori or will change over time. The proposed method first determines two quantizer cells and the corresponding output levels such that the distortion is minimized over all possible two-level quantizers. Then the cell with the largest empirical distortion is split into two cells in such a way that the empirical distortion is minimized over all possible splits. Each time a split is made, the number of output levels increases by one until the target number of cells is reached. Finally, the resultant quantizer serves as a good initial starting point for running the Lloyd-Max Algorithm in order to reach global optimality. Experimental results show that this new designed quantizer outperforms that obtained by the Lloyd-Max method started with an arbitrary initial point in terms of Mean Square Error (MSE). Moreover, the proposed method converges more rapidly than the Lloyd-Max one. Our method adapts itself to the histogram of the data without creating any empty output range. This feature improves the robustness of the design method.","PeriodicalId":442381,"journal":{"name":"2010 XIth International Workshop on Symbolic and Numerical Methods, Modeling and Applications to Circuit Design (SM2ACD)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131960784","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-12-17DOI: 10.1109/SM2ACD.2010.5672296
A. Ltifi, M. Ghariani, R. Neji
Non linear control of the squirrel induction motor propelling an Electric Vehicle (EV) is designed using sliding mode theory. The proposed scheme uses an adaptive flux and speed observer that is based on a full order model of the induction motor in the indirect vector-controlled drive. The sliding mode tools allow us to separate the control from these two outputs torque and flux. To take account of parametric variations, a model-based approach is used to improve the robustness of the control law despite these perturbations. Simulations were carried out on a test vehicle propelled by an induction motor to evaluate the consistency and the performance of the proposed control approach. The obtained results seem to be very promising.
{"title":"Sliding mode control of the nonlinear systems","authors":"A. Ltifi, M. Ghariani, R. Neji","doi":"10.1109/SM2ACD.2010.5672296","DOIUrl":"https://doi.org/10.1109/SM2ACD.2010.5672296","url":null,"abstract":"Non linear control of the squirrel induction motor propelling an Electric Vehicle (EV) is designed using sliding mode theory. The proposed scheme uses an adaptive flux and speed observer that is based on a full order model of the induction motor in the indirect vector-controlled drive. The sliding mode tools allow us to separate the control from these two outputs torque and flux. To take account of parametric variations, a model-based approach is used to improve the robustness of the control law despite these perturbations. Simulations were carried out on a test vehicle propelled by an induction motor to evaluate the consistency and the performance of the proposed control approach. The obtained results seem to be very promising.","PeriodicalId":442381,"journal":{"name":"2010 XIth International Workshop on Symbolic and Numerical Methods, Modeling and Applications to Circuit Design (SM2ACD)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127651438","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-12-17DOI: 10.1109/SM2ACD.2010.5672303
D. Zaum, Stefan Hoelldampf, M. Olbrich, E. Barke, I. Neumann
When simulating mixed-signal systems, designers are often dissatisfied either with performance or accuracy. A state-space based precomputation method for analog circuits at electrical level allows for a considerably faster simulation than with SPICE-like simulators. Utilizing an automatically generated SystemC interface, our simulation kernel analyzes mixed analog/digital circuits where the digital components are described on a higher level of abstraction than the analog parts. Results show a speedup of up to two orders of magnitude compared to mixed-signal simulation using ModelSim coupled with Saber or HSpice.
{"title":"SystemC mixed-signal and mixed-level simulation using an accelerated analog simulation approach","authors":"D. Zaum, Stefan Hoelldampf, M. Olbrich, E. Barke, I. Neumann","doi":"10.1109/SM2ACD.2010.5672303","DOIUrl":"https://doi.org/10.1109/SM2ACD.2010.5672303","url":null,"abstract":"When simulating mixed-signal systems, designers are often dissatisfied either with performance or accuracy. A state-space based precomputation method for analog circuits at electrical level allows for a considerably faster simulation than with SPICE-like simulators. Utilizing an automatically generated SystemC interface, our simulation kernel analyzes mixed analog/digital circuits where the digital components are described on a higher level of abstraction than the analog parts. Results show a speedup of up to two orders of magnitude compared to mixed-signal simulation using ModelSim coupled with Saber or HSpice.","PeriodicalId":442381,"journal":{"name":"2010 XIth International Workshop on Symbolic and Numerical Methods, Modeling and Applications to Circuit Design (SM2ACD)","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116148344","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-12-17DOI: 10.1109/SM2ACD.2010.5672366
C. Zorio, I. Rusu, M. Bodea
Using symbolic algorithms for small signal circuit parameter extraction could make possible implementing extraction programs which, unlike those based on pure numerical methods, no longer require initial (“start”) values for the parameters being extracted, thus ensuring that the final result corresponds to the true global minimum of the error function. Solving the extraction problem, in the particular case of a linear circuit, can be reduced to the math problem of determining the solutions of a system of polynomial equations. During resolution, classical mathematical algorithms used in the symbolic computing phase could generate during execution symbolic polynomials of size that could increase too fast (by a double exponential law) with the size of the input polynomials (thus making the symbolic computation useless), but in the case of specialized algorithms the size of intermediate polynomials could grow much slower (only by a polynomial law). An insight of the state of art of computational algebra can identify the main algorithms having good performance in terms of computational complexity to be used for symbolic variables elimination between the equations of a polynomial system. This paper analyzes, using a particular circuit, the performance of existing implementations for CAD math systems, which use symbolic methods based on different mathematical approaches, and compares the performances of these programs.
{"title":"An evaluation of symbolic computation algorithms for the extraction of small signal parameters of a linear circuit","authors":"C. Zorio, I. Rusu, M. Bodea","doi":"10.1109/SM2ACD.2010.5672366","DOIUrl":"https://doi.org/10.1109/SM2ACD.2010.5672366","url":null,"abstract":"Using symbolic algorithms for small signal circuit parameter extraction could make possible implementing extraction programs which, unlike those based on pure numerical methods, no longer require initial (“start”) values for the parameters being extracted, thus ensuring that the final result corresponds to the true global minimum of the error function. Solving the extraction problem, in the particular case of a linear circuit, can be reduced to the math problem of determining the solutions of a system of polynomial equations. During resolution, classical mathematical algorithms used in the symbolic computing phase could generate during execution symbolic polynomials of size that could increase too fast (by a double exponential law) with the size of the input polynomials (thus making the symbolic computation useless), but in the case of specialized algorithms the size of intermediate polynomials could grow much slower (only by a polynomial law). An insight of the state of art of computational algebra can identify the main algorithms having good performance in terms of computational complexity to be used for symbolic variables elimination between the equations of a polynomial system. This paper analyzes, using a particular circuit, the performance of existing implementations for CAD math systems, which use symbolic methods based on different mathematical approaches, and compares the performances of these programs.","PeriodicalId":442381,"journal":{"name":"2010 XIth International Workshop on Symbolic and Numerical Methods, Modeling and Applications to Circuit Design (SM2ACD)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129792324","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-12-17DOI: 10.1109/SM2ACD.2010.5672332
D. Boolchandani, L. Garg, S. Khandelwal, V. Sahula
During analog circuit synthesis in nanometer technology, process variability analysis is mandatory during design space exploration. This would ensure that the circuit will function as per specifications after fabrication even with impact of statistical variations in nanometer regimes. The methodology necessitates the evaluation of performance metrics of an analog circuit for different sizing instances of the transistors. Circuit simulation for performance evaluation is very time consuming and is seldom a choice while sizing a circuit for a chosen topology. The complexity of sizing methodology increases with the need to consider effects of variations in process and environment parameters. We employ macromodeling approach for analog circuits based on support vector machine (SVM), which enables efficient evaluation of performance of such circuits during sizing and yield optimization loops. The objective to improve evaluation efficiency has been the motivation behind efforts to develop performance macromodels, which should be as accurate as SPICE and at the same time have shorter evaluation time for use in the sizing of analog circuits, where they are used as substitutes for full circuit simulation during circuit sizing (synthesis). Process variability aware SVM macromodels are used in the multiobjective multivariate sizing method which is also yield optimal. Post design centering, the sized circuits will be able to provide functions as per specifications upon fabrication. Its application as process variability analysis tool is illustrated on two stage op amp and a voltage controlled oscillator using 90 nm BSIM4 models of transistors.
{"title":"Variability aware yield optimal sizing of analog circuits using SVM-genetic approach","authors":"D. Boolchandani, L. Garg, S. Khandelwal, V. Sahula","doi":"10.1109/SM2ACD.2010.5672332","DOIUrl":"https://doi.org/10.1109/SM2ACD.2010.5672332","url":null,"abstract":"During analog circuit synthesis in nanometer technology, process variability analysis is mandatory during design space exploration. This would ensure that the circuit will function as per specifications after fabrication even with impact of statistical variations in nanometer regimes. The methodology necessitates the evaluation of performance metrics of an analog circuit for different sizing instances of the transistors. Circuit simulation for performance evaluation is very time consuming and is seldom a choice while sizing a circuit for a chosen topology. The complexity of sizing methodology increases with the need to consider effects of variations in process and environment parameters. We employ macromodeling approach for analog circuits based on support vector machine (SVM), which enables efficient evaluation of performance of such circuits during sizing and yield optimization loops. The objective to improve evaluation efficiency has been the motivation behind efforts to develop performance macromodels, which should be as accurate as SPICE and at the same time have shorter evaluation time for use in the sizing of analog circuits, where they are used as substitutes for full circuit simulation during circuit sizing (synthesis). Process variability aware SVM macromodels are used in the multiobjective multivariate sizing method which is also yield optimal. Post design centering, the sized circuits will be able to provide functions as per specifications upon fabrication. Its application as process variability analysis tool is illustrated on two stage op amp and a voltage controlled oscillator using 90 nm BSIM4 models of transistors.","PeriodicalId":442381,"journal":{"name":"2010 XIth International Workshop on Symbolic and Numerical Methods, Modeling and Applications to Circuit Design (SM2ACD)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131982480","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-12-17DOI: 10.1109/SM2ACD.2010.5672338
T. Bentercia, F. Djeffal, M. Abdi, D. Arar
Due to the excellent control of DG MOSFETs over the short channel effects, they have been considered as a leading candidate to extend the scaling limit of conventional bulk MOSFETs. However, the hot carrier injection into gate oxides remains a potential problem in reliability field hence altering the device lifetime. In the present paper, a comprehensive drain current model incorporating hot-carrier-induced degradation effect is developed, the derivation is carried out based on some assumptions regarding threshold voltage and mobility. Using obtained model, we have studied the utility of adding a high-k layer into the device structure for which an improvement is detected, the accuracy and efficiency make our analytic current-voltage model for DG MOSFETs suitable for circuit simulation programs.
{"title":"A compact analytical current model including traps effects for GS DG MOSFETs","authors":"T. Bentercia, F. Djeffal, M. Abdi, D. Arar","doi":"10.1109/SM2ACD.2010.5672338","DOIUrl":"https://doi.org/10.1109/SM2ACD.2010.5672338","url":null,"abstract":"Due to the excellent control of DG MOSFETs over the short channel effects, they have been considered as a leading candidate to extend the scaling limit of conventional bulk MOSFETs. However, the hot carrier injection into gate oxides remains a potential problem in reliability field hence altering the device lifetime. In the present paper, a comprehensive drain current model incorporating hot-carrier-induced degradation effect is developed, the derivation is carried out based on some assumptions regarding threshold voltage and mobility. Using obtained model, we have studied the utility of adding a high-k layer into the device structure for which an improvement is detected, the accuracy and efficiency make our analytic current-voltage model for DG MOSFETs suitable for circuit simulation programs.","PeriodicalId":442381,"journal":{"name":"2010 XIth International Workshop on Symbolic and Numerical Methods, Modeling and Applications to Circuit Design (SM2ACD)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114081184","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-12-17DOI: 10.1109/SM2ACD.2010.5672346
C. Sánchez-López, R. Castro-López, E. Roca, F. Fernández, R. Gonzalez-Echevarria, J. Esteban-Muller, J. López-Villegas, J. Sieiro, N. Vidal
A systematic design methodology for low-noise amplifiers (LNAs) is introduced. This methodology follows a bottom-up approach that employs a multi-objective evolutionary optimization algorithm, which is used at two levels. First, it is used to generate Pareto-based performance models for integrated planar inductors. To do so, an electromagnetic simulator that takes into account the inductor's layout, thus providing highly accurate performance evaluations, is coupled to the optimizer. Unlike foundry-provided inductor libraries, these Pareto-based models offer a detailed insight of the trade-offs between inductance, quality factor and area. Afterwards the Pareto-based models for the inductors are used as design variables to generate the LNA Pareto surface, thus providing highly accurate performance trade-offs of the LNA.
{"title":"A bottom-up approach to the systematic design of LNAs using evolutionary optimization","authors":"C. Sánchez-López, R. Castro-López, E. Roca, F. Fernández, R. Gonzalez-Echevarria, J. Esteban-Muller, J. López-Villegas, J. Sieiro, N. Vidal","doi":"10.1109/SM2ACD.2010.5672346","DOIUrl":"https://doi.org/10.1109/SM2ACD.2010.5672346","url":null,"abstract":"A systematic design methodology for low-noise amplifiers (LNAs) is introduced. This methodology follows a bottom-up approach that employs a multi-objective evolutionary optimization algorithm, which is used at two levels. First, it is used to generate Pareto-based performance models for integrated planar inductors. To do so, an electromagnetic simulator that takes into account the inductor's layout, thus providing highly accurate performance evaluations, is coupled to the optimizer. Unlike foundry-provided inductor libraries, these Pareto-based models offer a detailed insight of the trade-offs between inductance, quality factor and area. Afterwards the Pareto-based models for the inductors are used as design variables to generate the LNA Pareto surface, thus providing highly accurate performance trade-offs of the LNA.","PeriodicalId":442381,"journal":{"name":"2010 XIth International Workshop on Symbolic and Numerical Methods, Modeling and Applications to Circuit Design (SM2ACD)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115812384","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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