C. Arvin, S. Lim, David Locker, W. K. Loh, K. Sweatman, Francis Lee, M. Tsuriya
{"title":"Low temperature interconnects in 1st level packaging and its challenges","authors":"C. Arvin, S. Lim, David Locker, W. K. Loh, K. Sweatman, Francis Lee, M. Tsuriya","doi":"10.23919/ICEP55381.2022.9795576","DOIUrl":null,"url":null,"abstract":"This paper reviews the materials and processes of 1st level interconnects and seeks to understand how utilization of low temperature materials can enable the future needs of 1st level packages. An industry survey was administered to understand the key drivers that necessitate the use of low temperature materials. These were incorporation of thermal sensitive components, utilization of advanced substrate materials, warpage control of thinned substrates / components and energy reduction. There were three approaches mentioned to incorporate these low temperature materials: 1) replace the interconnect materials completely with low temperature materials, 2) use traditional solders for attachment of certain items followed by second attachment steps using low temperature materials for thermal sensitive elements and 3) attach a component or die that has traditional SAC solder on it but has low temperature materials on the substrate side. Low melting point tin-bismuth alloys that have been introduced to board level assembly were highlighted as potential candidates for these 1st level interconnects. It had yet to be confirmed that properties of these alloys were consistent with the requirements of 1st level interconnects such as fine pitch connections near the processor. Concerns included alpha emissions, microstructural stability, susceptibility to electromigration, whisker growth, and possibility of polymorphic transformation of tin phase at cryogenic temperatures to which some processors might be exposed. For high frequency circuitry the inductance and capacitance properties of the interconnect materials also needed to be understood. Consideration was given to whether the low melting point indium alloys that have found application in the attachment of IR Focal Plane Arrays could be used for other devices. Where the properties of low melting point alloys might not be sufficient to cope with possible service conditions, post joining processes were discussed to convert the low melting point materials to a higher melting point final joint that were comprised substantially of intermetallic compounds.","PeriodicalId":413776,"journal":{"name":"2022 International Conference on Electronics Packaging (ICEP)","volume":"378 ","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-05-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 International Conference on Electronics Packaging (ICEP)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.23919/ICEP55381.2022.9795576","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
This paper reviews the materials and processes of 1st level interconnects and seeks to understand how utilization of low temperature materials can enable the future needs of 1st level packages. An industry survey was administered to understand the key drivers that necessitate the use of low temperature materials. These were incorporation of thermal sensitive components, utilization of advanced substrate materials, warpage control of thinned substrates / components and energy reduction. There were three approaches mentioned to incorporate these low temperature materials: 1) replace the interconnect materials completely with low temperature materials, 2) use traditional solders for attachment of certain items followed by second attachment steps using low temperature materials for thermal sensitive elements and 3) attach a component or die that has traditional SAC solder on it but has low temperature materials on the substrate side. Low melting point tin-bismuth alloys that have been introduced to board level assembly were highlighted as potential candidates for these 1st level interconnects. It had yet to be confirmed that properties of these alloys were consistent with the requirements of 1st level interconnects such as fine pitch connections near the processor. Concerns included alpha emissions, microstructural stability, susceptibility to electromigration, whisker growth, and possibility of polymorphic transformation of tin phase at cryogenic temperatures to which some processors might be exposed. For high frequency circuitry the inductance and capacitance properties of the interconnect materials also needed to be understood. Consideration was given to whether the low melting point indium alloys that have found application in the attachment of IR Focal Plane Arrays could be used for other devices. Where the properties of low melting point alloys might not be sufficient to cope with possible service conditions, post joining processes were discussed to convert the low melting point materials to a higher melting point final joint that were comprised substantially of intermetallic compounds.