Common Source Inductance Compensation Technique for Dynamic Current Balancing in SiC MOSFETs Parallel Operations

Abstract

In high-current applications such as traction inverters, SiC MOSFETs are paralleled to increase the current capability. One major issue in paralleling SiC MOSFETs is the dynamic current unbalance. The unbalanced dynamic current could lead to severe device and system failures. It was well known that one of the root causes of dynamic current unbalance is parasitic parameter unbalance due to asymmetrical layout. In this paper, the impact of different parasitic parameters in circuit layout on current sharing is identified. Based on the analysis, a common source inductance (CSI) compensation technique is proposed for SiC MOSFETs in parallel operations to balance the dynamic current during the switching transient. With the proposed technique, the dynamic current among paralleled switches is evenly distributed even when the layout is not symmetrical. The improved current sharing is achieved by designing the common source inductance of each paralleled device inversely proportional to the power loop inductance. Because of the balanced dynamic current, the reliability of the circuit with the proposed layout can be significantly improved. The proposed technique is an easy-to-implement design that requires no additional components. Two types of prototypes are built to verify the proposed technique: A half-bridge configuration with SiC discrete devices in parallel and a multi-chip power module with SiC dies in parallel. The proposed technique is proven effective in both cases.