Mechanisms of high hole mobility in (100) nanowire pMOSFETs with width of less than 10nm

H. Nomura, R. Suzuki, T. Kutsuki, T. Saraya, T. Hiramoto
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引用次数: 2

Abstract

The mechanism of high mobility in <;110>;-directed nanowire pMOSFETs with height of 10nm on (100) SOI substrate is investigated. The 9nm-wide nanowire pFET has higher mobility than the (100) universal mobility at 300K The temperature dependence measurements of hole mobility show that the high mobility in nanowire pFET originates from the effect of (110) side surface of the nanowire. On the other hand, it is shown that the degraded mobility in 4nm-wide nanowire pFET is caused by the increase in surface roughness scattering.
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宽度小于10nm的(100)纳米线pmosfet的高空穴迁移率机制
研究了在(100)SOI衬底上制备高度为10nm的定向纳米线pmosfet的高迁移率机理。在300K时,9nm宽的纳米线pFET的迁移率比(100)通用迁移率高。空穴迁移率的温度依赖性测量表明,纳米线pFET的高迁移率源于纳米线(110)侧表面的影响。另一方面,在4nm宽的纳米线fet中,迁移率的下降是由于表面粗糙度散射的增加引起的。
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