Pub Date : 2012-03-06DOI: 10.1109/ULIS.2012.6193385
S. Morvan, F. Andrieu, M. Cassé, P. Nguyen, O. Weber, P. Perreau, C. Tabone, F. Allain, A. Toffoli, G. Ghibaudo, T. Poiroux
We fabricated highly stressed FDSOI nMOSFETs down to 18nm gate length. The impact of different stressors (CESL, STI) is studied for different device geometries and substrates orientation (<;100>; or <;110>;). We evidence that STI degrades wide devices of intermediate gate length (0.2μm<;LG<;1μm) along <;100>; compared to <;110>; (-20% mobility) whereas short nMOSFETs are improved along <;100>; with a (1.6 GPa) tensile CESL (+15% mobility, +6% ION). The CESL-induced mobility enhancement can be reproduced rather well for the two channel orientations by the piezo-resistive model and an analytical model of the stress profile.
{"title":"Comparison between <100> and <110> oriented channels in highly strained FDSOI nMOSFETs","authors":"S. Morvan, F. Andrieu, M. Cassé, P. Nguyen, O. Weber, P. Perreau, C. Tabone, F. Allain, A. Toffoli, G. Ghibaudo, T. Poiroux","doi":"10.1109/ULIS.2012.6193385","DOIUrl":"https://doi.org/10.1109/ULIS.2012.6193385","url":null,"abstract":"We fabricated highly stressed FDSOI nMOSFETs down to 18nm gate length. The impact of different stressors (CESL, STI) is studied for different device geometries and substrates orientation (<;100>; or <;110>;). We evidence that STI degrades wide devices of intermediate gate length (0.2μm<;LG<;1μm) along <;100>; compared to <;110>; (-20% mobility) whereas short nMOSFETs are improved along <;100>; with a (1.6 GPa) tensile CESL (+15% mobility, +6% ION). The CESL-induced mobility enhancement can be reproduced rather well for the two channel orientations by the piezo-resistive model and an analytical model of the stress profile.","PeriodicalId":350544,"journal":{"name":"2012 13th International Conference on Ultimate Integration on Silicon (ULIS)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115067993","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-06DOI: 10.1109/ULIS.2012.6193353
L. Knoll, A. Schafer, S. Trellenkamp, K. Bourdelle, Q. Zhao, S. Mantl
Schottky Barrier MOSFETs were fabricated on ultra thin body (UTB) SOI with planar and NW-array device geometry. Implantation into Silicide (IIS) was used to lower the Schottky Barrier height for n- and p-type MOSFETs. The enhanced gate control of the NW array reduces Drain Induced Barrier Lowering (DIBL) and improves the subthreshold slope in n-type MOSFETs, whereas the corrected current drops. In p-type MOSFETs on current and Ion/Ioff ratio is enhanced.
{"title":"Nanowire and planar UTB SOI Schottky Barrier MOSFETs with dopant segregation","authors":"L. Knoll, A. Schafer, S. Trellenkamp, K. Bourdelle, Q. Zhao, S. Mantl","doi":"10.1109/ULIS.2012.6193353","DOIUrl":"https://doi.org/10.1109/ULIS.2012.6193353","url":null,"abstract":"Schottky Barrier MOSFETs were fabricated on ultra thin body (UTB) SOI with planar and NW-array device geometry. Implantation into Silicide (IIS) was used to lower the Schottky Barrier height for n- and p-type MOSFETs. The enhanced gate control of the NW array reduces Drain Induced Barrier Lowering (DIBL) and improves the subthreshold slope in n-type MOSFETs, whereas the corrected current drops. In p-type MOSFETs on current and Ion/Ioff ratio is enhanced.","PeriodicalId":350544,"journal":{"name":"2012 13th International Conference on Ultimate Integration on Silicon (ULIS)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122418760","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-06DOI: 10.1109/ULIS.2012.6193377
M. Vacca, M. Graziano, D. Demarchi, G. Piccinini
Ultra Deep Sub-Micron (UDSM) processes, as well as beyond CMOS technology choices, influence circuits performance with a chain of consequences through devices, circuits and systems that are difficult to predict. Nonetheless effective design-space exploration enables process optimization and early design organization. We introduce TAMTAMS, a tool based on an open, flexible and simple structure, which allows to predict system level features starting from technology variables. It is modular and based on a clear dependency tree of modules, each related to a model of specific quantities (e.g. device currents, circuit delay, interconnects noise, ....) presented in literature. Models can be compared and sensitivity to parameters observed. We believe our contribution gives a fresh point of view on process-to-system predictors. Though still in development, it already shows flexibility and allows a traceable path of a technology parameter on its way to the system level.
{"title":"TAMTAMS: A flexible and open tool for UDSM process-to-system design space exploration","authors":"M. Vacca, M. Graziano, D. Demarchi, G. Piccinini","doi":"10.1109/ULIS.2012.6193377","DOIUrl":"https://doi.org/10.1109/ULIS.2012.6193377","url":null,"abstract":"Ultra Deep Sub-Micron (UDSM) processes, as well as beyond CMOS technology choices, influence circuits performance with a chain of consequences through devices, circuits and systems that are difficult to predict. Nonetheless effective design-space exploration enables process optimization and early design organization. We introduce TAMTAMS, a tool based on an open, flexible and simple structure, which allows to predict system level features starting from technology variables. It is modular and based on a clear dependency tree of modules, each related to a model of specific quantities (e.g. device currents, circuit delay, interconnects noise, ....) presented in literature. Models can be compared and sensitivity to parameters observed. We believe our contribution gives a fresh point of view on process-to-system predictors. Though still in development, it already shows flexibility and allows a traceable path of a technology parameter on its way to the system level.","PeriodicalId":350544,"journal":{"name":"2012 13th International Conference on Ultimate Integration on Silicon (ULIS)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114293832","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-06DOI: 10.1109/ULIS.2012.6193369
S. Makovejev, S. Olsen, F. Andrieu, T. Poiroux, O. Faynot, D. Flandre, J. Raskin, V. Kilchytska
In this work UTBB devices with different BOX thicknesses of 10 and 25 nm are compared in terms of self-heating (SH) effect Different approaches of SH characterisation are assessed. Strengths and weaknesses of every extraction technique when applied to advanced UTBB MOSFETs are discussed. We show that while thermal effects are important even in devices with ultra-thin BOX, the resulting drain current degradation is not severe and is not considerably affected by BOX thickening from 10 to 25 nm. The main SH-related issue is output conductance degradation, which is of great importance for analogue applications.
{"title":"On extraction of self-heating features in UTBB SOI MOSFETs","authors":"S. Makovejev, S. Olsen, F. Andrieu, T. Poiroux, O. Faynot, D. Flandre, J. Raskin, V. Kilchytska","doi":"10.1109/ULIS.2012.6193369","DOIUrl":"https://doi.org/10.1109/ULIS.2012.6193369","url":null,"abstract":"In this work UTBB devices with different BOX thicknesses of 10 and 25 nm are compared in terms of self-heating (SH) effect Different approaches of SH characterisation are assessed. Strengths and weaknesses of every extraction technique when applied to advanced UTBB MOSFETs are discussed. We show that while thermal effects are important even in devices with ultra-thin BOX, the resulting drain current degradation is not severe and is not considerably affected by BOX thickening from 10 to 25 nm. The main SH-related issue is output conductance degradation, which is of great importance for analogue applications.","PeriodicalId":350544,"journal":{"name":"2012 13th International Conference on Ultimate Integration on Silicon (ULIS)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122081890","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-06DOI: 10.1109/ULIS.2012.6193387
Y. Leblebici
Next generation logic switching devices are expected to rely on radically new technologies mainly due to the increasing difficulties and limitations of state-of-the-art CMOS switches, which, in turn, will also require innovative circuit and system architectures, and design methodologies that are distinctly different from those used for CMOS technologies. In this paper, we discuss a few specific examples of logic design platforms that exploit the structural regularity that is predicted to dominate SiNW based systems, as well as the ambipolarity of devices that can be utilized to achieve higher logic versatility for the same number of components.
{"title":"Nanometer-scale system design challenges: Bridging the gap from devices to architectures","authors":"Y. Leblebici","doi":"10.1109/ULIS.2012.6193387","DOIUrl":"https://doi.org/10.1109/ULIS.2012.6193387","url":null,"abstract":"Next generation logic switching devices are expected to rely on radically new technologies mainly due to the increasing difficulties and limitations of state-of-the-art CMOS switches, which, in turn, will also require innovative circuit and system architectures, and design methodologies that are distinctly different from those used for CMOS technologies. In this paper, we discuss a few specific examples of logic design platforms that exploit the structural regularity that is predicted to dominate SiNW based systems, as well as the ambipolarity of devices that can be utilized to achieve higher logic versatility for the same number of components.","PeriodicalId":350544,"journal":{"name":"2012 13th International Conference on Ultimate Integration on Silicon (ULIS)","volume":"187 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126901445","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-06DOI: 10.1109/ULIS.2012.6193365
D. Jiménez, O. Moldovan
We present a compact physics-based model of the current-voltage characteristics of graphene field-effect transistors, of especial interest for analog and radio-frequency applications where bandgap engineering of graphene could be not needed. The physical framework is a field-effect model and drift-diffusion carrier transport. Explicit closed-form expressions have been derived for the drain current covering continuosly all operation regions. The model has been benchmarked with measured prototype devices, demonstrating accuracy and predictive behavior.
{"title":"Theory of graphene-field effect transistors","authors":"D. Jiménez, O. Moldovan","doi":"10.1109/ULIS.2012.6193365","DOIUrl":"https://doi.org/10.1109/ULIS.2012.6193365","url":null,"abstract":"We present a compact physics-based model of the current-voltage characteristics of graphene field-effect transistors, of especial interest for analog and radio-frequency applications where bandgap engineering of graphene could be not needed. The physical framework is a field-effect model and drift-diffusion carrier transport. Explicit closed-form expressions have been derived for the drain current covering continuosly all operation regions. The model has been benchmarked with measured prototype devices, demonstrating accuracy and predictive behavior.","PeriodicalId":350544,"journal":{"name":"2012 13th International Conference on Ultimate Integration on Silicon (ULIS)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132139051","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-06DOI: 10.1109/ULIS.2012.6193373
P. Razavi, I. Ferain, Samaresh Das, R. Yu, N. Akhavan, J. Colinge
In this paper we investigate two important device metrics, intrinsic gate-delay and energy-delay product of triple-gate junctionless nanowire transistors (JNTs) with gate lengths from 22 nm down to 15 nm, for different channel doping concentrations and compare them with those of triple-gate inversion-mode (EVI) nanowire field-effect transistors. Our study shows although intrinsic gate-delay is larger in junctionless devices compared to those of EVI devices, since the switching energy is smaller in JNTs, energy-delay product is almost identical for both junctionless and IM devices.
{"title":"Intrinsic gate delay and energy-delay product in junctionless nanowire transistors","authors":"P. Razavi, I. Ferain, Samaresh Das, R. Yu, N. Akhavan, J. Colinge","doi":"10.1109/ULIS.2012.6193373","DOIUrl":"https://doi.org/10.1109/ULIS.2012.6193373","url":null,"abstract":"In this paper we investigate two important device metrics, intrinsic gate-delay and energy-delay product of triple-gate junctionless nanowire transistors (JNTs) with gate lengths from 22 nm down to 15 nm, for different channel doping concentrations and compare them with those of triple-gate inversion-mode (EVI) nanowire field-effect transistors. Our study shows although intrinsic gate-delay is larger in junctionless devices compared to those of EVI devices, since the switching energy is smaller in JNTs, energy-delay product is almost identical for both junctionless and IM devices.","PeriodicalId":350544,"journal":{"name":"2012 13th International Conference on Ultimate Integration on Silicon (ULIS)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114798499","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-06DOI: 10.1109/ULIS.2012.6193350
W. Haensch
Conventional CMOS scaling is rapidly coming to an end and the quest for solutions is in full swing how to meet the computational demands for the foreseeable future. Possible solutions are the change of device architecture and the introduction of high mobility materials for the devices. Beyond the classical device materials Si, Ge, and some III/V compounds carbon in the form of carbon nano tubes seems to provide an interesting alternative for digital applications.
{"title":"High performance computing beyond 14nm node — Is there anything other than Si?","authors":"W. Haensch","doi":"10.1109/ULIS.2012.6193350","DOIUrl":"https://doi.org/10.1109/ULIS.2012.6193350","url":null,"abstract":"Conventional CMOS scaling is rapidly coming to an end and the quest for solutions is in full swing how to meet the computational demands for the foreseeable future. Possible solutions are the change of device architecture and the introduction of high mobility materials for the devices. Beyond the classical device materials Si, Ge, and some III/V compounds carbon in the form of carbon nano tubes seems to provide an interesting alternative for digital applications.","PeriodicalId":350544,"journal":{"name":"2012 13th International Conference on Ultimate Integration on Silicon (ULIS)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124685618","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-06DOI: 10.1109/ULIS.2012.6193354
Y. Niquet, C. Delerue, D. Rideau
We discuss the phonon-limited mobility of electrons and holes in silicon nanowires as a function of diameter and orientation. We show that 〈110〉 and 〈001〉 nanowires are the best n-type channels, while 〈110〉 and 〈111〉 nanowires are the best p-type channels. We also investigate the mobility in stretched silicon nanowires. We show that the electron and hole mobility can be enhanced or reduced by a factor >; 2 for moderate axial strains <; 1%.
{"title":"Orientational and strain dependence of the mobility in silicon nanowires","authors":"Y. Niquet, C. Delerue, D. Rideau","doi":"10.1109/ULIS.2012.6193354","DOIUrl":"https://doi.org/10.1109/ULIS.2012.6193354","url":null,"abstract":"We discuss the phonon-limited mobility of electrons and holes in silicon nanowires as a function of diameter and orientation. We show that 〈110〉 and 〈001〉 nanowires are the best n-type channels, while 〈110〉 and 〈111〉 nanowires are the best p-type channels. We also investigate the mobility in stretched silicon nanowires. We show that the electron and hole mobility can be enhanced or reduced by a factor >; 2 for moderate axial strains <; 1%.","PeriodicalId":350544,"journal":{"name":"2012 13th International Conference on Ultimate Integration on Silicon (ULIS)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126851967","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-06DOI: 10.1109/ULIS.2012.6193357
L. Almeida, M. Aoulaiche, K. Sasaki, T. Nicoletti, M. G. C. de Andrade, N. Collaert, E. Simoen, C. Claeys, J. Martino, M. Jurczak
This paper investigates the drain read bias impact on the FB-BRAM performance of Ultra Thin Buried Oxide (UTBOX) Fully Depleted Silicon On Insulator (FDSOI) devices. Both simulations and experimental results are used. Two read regimes are clearly observed. In the read regime at higher drain voltage, impact ionization is occurring and this result in a higher sense margin and a lower retention time compared to the low drain voltage read regime.
{"title":"Comparison between low and high read bias in FB-RAM on UTBOX FDSOI devices","authors":"L. Almeida, M. Aoulaiche, K. Sasaki, T. Nicoletti, M. G. C. de Andrade, N. Collaert, E. Simoen, C. Claeys, J. Martino, M. Jurczak","doi":"10.1109/ULIS.2012.6193357","DOIUrl":"https://doi.org/10.1109/ULIS.2012.6193357","url":null,"abstract":"This paper investigates the drain read bias impact on the FB-BRAM performance of Ultra Thin Buried Oxide (UTBOX) Fully Depleted Silicon On Insulator (FDSOI) devices. Both simulations and experimental results are used. Two read regimes are clearly observed. In the read regime at higher drain voltage, impact ionization is occurring and this result in a higher sense margin and a lower retention time compared to the low drain voltage read regime.","PeriodicalId":350544,"journal":{"name":"2012 13th International Conference on Ultimate Integration on Silicon (ULIS)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123338343","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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