D. Tang, W. Lin, L. Lai, C. Wang, L.P. Lee, H.M. Hsu, C. Wu, C.W. Chang, W. Lien, C. Chao, C. Lee, G. J. Chern, J. Guo, C. Chang, Y.C. Sun, D. Du, K. Lan, L. Lin
{"title":"The integration of proton bombardment process into the manufacturing of mixed-signal/RF chips","authors":"D. Tang, W. Lin, L. Lai, C. Wang, L.P. Lee, H.M. Hsu, C. Wu, C.W. Chang, W. Lien, C. Chao, C. Lee, G. J. Chern, J. Guo, C. Chang, Y.C. Sun, D. Du, K. Lan, L. Lin","doi":"10.1109/IEDM.2003.1269370","DOIUrl":null,"url":null,"abstract":"Proton bombardment technology is integrated into the standard IC process as a post-backend process module to form local semi-insulating regions on mixed-signal/RF chips. With 10/sup 15/ cm/sup -2/, 100 /spl mu/m deep bombardment through mask windows, /spl rho//sub s/=20k/spl sim/50k /spl Omega/.cm regions are formed, which are thermally stable at 200/spl deg/C. High-Q inductors and reliable MOSFETs are made on same chip with no need of tuning the existing wafer process. Design rules are established.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"14 1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE International Electron Devices Meeting 2003","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.2003.1269370","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 8
Abstract
Proton bombardment technology is integrated into the standard IC process as a post-backend process module to form local semi-insulating regions on mixed-signal/RF chips. With 10/sup 15/ cm/sup -2/, 100 /spl mu/m deep bombardment through mask windows, /spl rho//sub s/=20k/spl sim/50k /spl Omega/.cm regions are formed, which are thermally stable at 200/spl deg/C. High-Q inductors and reliable MOSFETs are made on same chip with no need of tuning the existing wafer process. Design rules are established.
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