A narrative of UVM testbench environment for interconnection routers: A practical approach

Abstract

In contrast to past projections using conventional bus-based interconnections, the use of Network on Chip (NoC) as an interconnection platform has become more promising to solve complex on-chip communication problems due to what it offers from scalability, reusability and efficiency. Moreover, providing a suitable test base to inspect and verify functionality of any IP core is a compulsory stage. To elaborate; Universal Verification Methodology (UVM) is introduced as a standardized and reusable methodology for verifying integrated circuit designs. In this paper, we present an architecture of a complete UVM environment to test generic routers through various test cases providing different scenarios to be applied. We also aim to establish a base on which other researchers can build to proceed towards finding better solutions.