Pub Date : 2016-12-18DOI: 10.1109/IDT.2016.7843052
Kaouthar Djemel, D. Moalla, Rahma Aloulou Hajtaieb, D. Cordeau, H. Mnif, J. Paillot, M. Loulou
The beamforming allowing the angle control for transmitted and received signals, is one of the most important challenge for the next generation of radio communication systems. Indeed a key point for the development of radio communication systems is to propose an electronic system associated with an antenna array architecture able to orientate the communications in the best direction. For this, magnitude and phase ponderations have to be applied on each antenna to assume the beamforming. Among the different solutions we find multi antenna arrays, which can be controlled by using oscillator arrays. In this context, this paper presents performances analysis in terms of sensitivity of the phase shift for different components of differential oscillators using the contour graph approach.
{"title":"Performances analysis of a coupled differential oscillators network using the contour graph approach","authors":"Kaouthar Djemel, D. Moalla, Rahma Aloulou Hajtaieb, D. Cordeau, H. Mnif, J. Paillot, M. Loulou","doi":"10.1109/IDT.2016.7843052","DOIUrl":"https://doi.org/10.1109/IDT.2016.7843052","url":null,"abstract":"The beamforming allowing the angle control for transmitted and received signals, is one of the most important challenge for the next generation of radio communication systems. Indeed a key point for the development of radio communication systems is to propose an electronic system associated with an antenna array architecture able to orientate the communications in the best direction. For this, magnitude and phase ponderations have to be applied on each antenna to assume the beamforming. Among the different solutions we find multi antenna arrays, which can be controlled by using oscillator arrays. In this context, this paper presents performances analysis in terms of sensitivity of the phase shift for different components of differential oscillators using the contour graph approach.","PeriodicalId":131600,"journal":{"name":"2016 11th International Design & Test Symposium (IDT)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134570010","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IDT.2016.7843017
N. Abid, T. Ouni, K. Loukil, M. Abid, A. Ammeri
The covariance region descriptor has been proved robust in person detection application. However, detection is difficult to achieve on a serial processor. This is due to the large data set required to represent the image and the complex operations that need to be performed on the image. Multiprocessor systems (MPSoC) are usually adopted to speed up such application. In this paper, we propose a novel MPSoC architecture for fast person detection based on covariance descriptor. For this end, an optimized Khan Process Network parallel model of a covariance person detection application and the Sesame design and space exploration framework are used. Based on the optimal parallel model of covariance based person detection application, a multiprocessor architecture model is first proposed. These two models are modeled and validated using Sesame simulation. After that, the mapping of application tasks and channels on the architecture components is explored to define the optimal mapping architecture using execution time and platform cost. Results show that the six processors based architecture is the best when looking for the low computation cost and the four processors based architecture is the best when looking for the low cost.
{"title":"Multiprocessor architecture for an optimazed parallel model of covariance based person detection","authors":"N. Abid, T. Ouni, K. Loukil, M. Abid, A. Ammeri","doi":"10.1109/IDT.2016.7843017","DOIUrl":"https://doi.org/10.1109/IDT.2016.7843017","url":null,"abstract":"The covariance region descriptor has been proved robust in person detection application. However, detection is difficult to achieve on a serial processor. This is due to the large data set required to represent the image and the complex operations that need to be performed on the image. Multiprocessor systems (MPSoC) are usually adopted to speed up such application. In this paper, we propose a novel MPSoC architecture for fast person detection based on covariance descriptor. For this end, an optimized Khan Process Network parallel model of a covariance person detection application and the Sesame design and space exploration framework are used. Based on the optimal parallel model of covariance based person detection application, a multiprocessor architecture model is first proposed. These two models are modeled and validated using Sesame simulation. After that, the mapping of application tasks and channels on the architecture components is explored to define the optimal mapping architecture using execution time and platform cost. Results show that the six processors based architecture is the best when looking for the low computation cost and the four processors based architecture is the best when looking for the low cost.","PeriodicalId":131600,"journal":{"name":"2016 11th International Design & Test Symposium (IDT)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116804727","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IDT.2016.7843003
Z. Marrakchi, Eman El Mandouh
Software has come to dominate system-on-chip (SoC) development. It is increasingly common for the software effort to be on the critical path of the project schedule. Only FPGA-based prototyping provides both the speed and accuracy necessary to develop and validate complex software integration prior to silicon. The exciting benefits of an FPGA-based prototype are: • Quick fine tuning of hardware/software integration and software validation pre-silicon • In-system device validation with real-time interfaces and in end application • Extended register transfer level (RTL) testing and debugging
{"title":"Tutorial 2: “Challenges of FPGA-based prototyping & debugging”","authors":"Z. Marrakchi, Eman El Mandouh","doi":"10.1109/IDT.2016.7843003","DOIUrl":"https://doi.org/10.1109/IDT.2016.7843003","url":null,"abstract":"Software has come to dominate system-on-chip (SoC) development. It is increasingly common for the software effort to be on the critical path of the project schedule. Only FPGA-based prototyping provides both the speed and accuracy necessary to develop and validate complex software integration prior to silicon. The exciting benefits of an FPGA-based prototype are: • Quick fine tuning of hardware/software integration and software validation pre-silicon • In-system device validation with real-time interfaces and in end application • Extended register transfer level (RTL) testing and debugging","PeriodicalId":131600,"journal":{"name":"2016 11th International Design & Test Symposium (IDT)","volume":"256 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121237747","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IDT.2016.7843036
M. Aseeri, A. A. Alasows, Muhammad R. Ahmad
Advanced digital RF memory is a key segment of the electronic jammer. A Digital Radio Frequency Memory (DRFM) framework is intended to digitize a Radio Frequency (RF) information signal at a particular recurrence and transmission capacity to communicate by radio signals and reproduce that RF signal after a progression of procedure. The equipment design for DRFM is based on the FPGA strategies. Because of a sensible division of the practical module, the general force utilization is low. However, web redesigning and active stacking of the FPGA project can be effectively accomplished through a serial fringe interface (SFI) for operations. This edge has been connected to the radar misleading jammer framework, which is genuinely legitimate. The DRFM has the capacity store radio and the microwave signal. The design is built on a critical segment of the advanced radar system. Thus, the DRFM can deal with the method, which is connected to the electronic countermeasure for the radio recurrent source. Firstly, this paper presents the order, making, and operation of DRFM based on FPGA framework. As indicated by configuration strategy, this paper discussed the DRFM system design taking into account the field programmable door cluster. The example rate, we selected for the displayed plan is 1 GHz and the specimen accuracy is 12 bits. We provided four ADC (250 MHz) parallel patterns to achieve 1 GSPS. In the single channel, we utilized the orthogonal computerized technology for the reasonable location, keeping in mind the goal to protect the data of the envelope signal. The field programmable gateway is connected to this framework to support control and data storage. Secondly, the Very High Speed Hardware Description Language (VHDL) is utilized to understand the configuration of DRFM circuit in light of the FPGA and the capacity reenactment and the succession examination. Large portions of the Low-Voltage Differential Signaling (LVDS) chip are utilized as a part of the framework, so the force of the DRFM is lessened significantly and the security of the framework is improved. Finally, in this paper, the computerized signal-preparing calculation that used in the configuration has carried on the reenactment; the outcome has demonstrated the outline feasibility. Thus, the DRFM framework taking into account FPGA has the highest execution list and the predominance.
先进的数字射频存储器是电子干扰机的关键部分。数字射频存储器(DRFM)框架旨在以特定的重复和传输能力将射频(RF)信息信号数字化，以通过无线电信号进行通信，并在一系列程序后再现该射频信号。DRFM的设备设计基于FPGA策略。由于对实用模块的合理划分，一般的兵力利用率较低。然而，通过串行条纹接口(SFI)进行操作，可以有效地完成FPGA项目的web重新设计和主动堆叠。这个边缘已经连接到雷达误导干扰机框架，这是真正合法的。DRFM具有存储无线电和微波信号的能力。该设计建立在先进雷达系统的关键部分上。因此，DRFM可以处理该方法，该方法与无线电再发源的电子对抗相连接。本文首先介绍了基于FPGA框架的DRFM的顺序、制作和操作。根据组态策略，讨论了考虑现场可编程门集群的DRFM系统设计。我们为显示方案选择的示例速率为1ghz，样本精度为12位。我们提供了四个ADC (250 MHz)并行模式来实现1 GSPS。在单信道中，我们利用正交计算机化技术进行合理的定位，同时考虑到保护包络信号数据的目的。现场可编程网关连接到该框架以支持控制和数据存储。其次，利用VHDL (Very High Speed Hardware Description Language)语言，结合FPGA了解DRFM电路的配置，并进行容量再现和接续检查。利用低压差分信号(LVDS)芯片的大部分作为框架的一部分，大大降低了DRFM的力，提高了框架的安全性。最后，本文对配置中使用的计算机信号准备计算进行了仿真;结果证明了该方法的可行性。因此，考虑FPGA的DRFM框架具有最高的执行列表和优势。
{"title":"Design of DRFM system based on FPGA with high resources","authors":"M. Aseeri, A. A. Alasows, Muhammad R. Ahmad","doi":"10.1109/IDT.2016.7843036","DOIUrl":"https://doi.org/10.1109/IDT.2016.7843036","url":null,"abstract":"Advanced digital RF memory is a key segment of the electronic jammer. A Digital Radio Frequency Memory (DRFM) framework is intended to digitize a Radio Frequency (RF) information signal at a particular recurrence and transmission capacity to communicate by radio signals and reproduce that RF signal after a progression of procedure. The equipment design for DRFM is based on the FPGA strategies. Because of a sensible division of the practical module, the general force utilization is low. However, web redesigning and active stacking of the FPGA project can be effectively accomplished through a serial fringe interface (SFI) for operations. This edge has been connected to the radar misleading jammer framework, which is genuinely legitimate. The DRFM has the capacity store radio and the microwave signal. The design is built on a critical segment of the advanced radar system. Thus, the DRFM can deal with the method, which is connected to the electronic countermeasure for the radio recurrent source. Firstly, this paper presents the order, making, and operation of DRFM based on FPGA framework. As indicated by configuration strategy, this paper discussed the DRFM system design taking into account the field programmable door cluster. The example rate, we selected for the displayed plan is 1 GHz and the specimen accuracy is 12 bits. We provided four ADC (250 MHz) parallel patterns to achieve 1 GSPS. In the single channel, we utilized the orthogonal computerized technology for the reasonable location, keeping in mind the goal to protect the data of the envelope signal. The field programmable gateway is connected to this framework to support control and data storage. Secondly, the Very High Speed Hardware Description Language (VHDL) is utilized to understand the configuration of DRFM circuit in light of the FPGA and the capacity reenactment and the succession examination. Large portions of the Low-Voltage Differential Signaling (LVDS) chip are utilized as a part of the framework, so the force of the DRFM is lessened significantly and the security of the framework is improved. Finally, in this paper, the computerized signal-preparing calculation that used in the configuration has carried on the reenactment; the outcome has demonstrated the outline feasibility. Thus, the DRFM framework taking into account FPGA has the highest execution list and the predominance.","PeriodicalId":131600,"journal":{"name":"2016 11th International Design & Test Symposium (IDT)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127299245","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IDT.2016.7843028
A. Mkhinini, P. Maistri, R. Leveugle, R. Tourki, Mohsen Machhout
In the era of the cloud computing, homomorphic encryption allows remote data processing while preserving confidentiality. Its main drawback, however, is the huge complexity in terms of operand size and computation time, which makes hardware acceleration desirable in order to achieve acceptable performance. In this paper, we present a flexible modular polynomial multiplier implemented through a high-level synthesis flow. We show that flexibility does not come at a price, and the proposed solution is competitive against custom designs.
{"title":"A flexible RNS-based large polynomial multiplier for Fully Homomorphic Encryption","authors":"A. Mkhinini, P. Maistri, R. Leveugle, R. Tourki, Mohsen Machhout","doi":"10.1109/IDT.2016.7843028","DOIUrl":"https://doi.org/10.1109/IDT.2016.7843028","url":null,"abstract":"In the era of the cloud computing, homomorphic encryption allows remote data processing while preserving confidentiality. Its main drawback, however, is the huge complexity in terms of operand size and computation time, which makes hardware acceleration desirable in order to achieve acceptable performance. In this paper, we present a flexible modular polynomial multiplier implemented through a high-level synthesis flow. We show that flexibility does not come at a price, and the proposed solution is competitive against custom designs.","PeriodicalId":131600,"journal":{"name":"2016 11th International Design & Test Symposium (IDT)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123273963","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IDT.2016.7843039
I. Bennour
SystemC has been developed as a standard system level language intended to enable transaction level modeling (TLM) and intellectual properties (IPs) exchange at multiple abstraction levels. To re-use formal analysis and verification methods on a SystemC code, the code has to be translated to a formal representation. Petri net is one of several mathematical modeling languages for the description of communication protocols and programs written with process-oriented parallel languages. In a previous work we dealt with the translation of a SystemC TLM module to Petri net. In this paper, we extend the translation to verify the TLM2 protocol consistency used by a module.
{"title":"SystemC TLM2-protocol consistency checker using Petri net","authors":"I. Bennour","doi":"10.1109/IDT.2016.7843039","DOIUrl":"https://doi.org/10.1109/IDT.2016.7843039","url":null,"abstract":"SystemC has been developed as a standard system level language intended to enable transaction level modeling (TLM) and intellectual properties (IPs) exchange at multiple abstraction levels. To re-use formal analysis and verification methods on a SystemC code, the code has to be translated to a formal representation. Petri net is one of several mathematical modeling languages for the description of communication protocols and programs written with process-oriented parallel languages. In a previous work we dealt with the translation of a SystemC TLM module to Petri net. In this paper, we extend the translation to verify the TLM2 protocol consistency used by a module.","PeriodicalId":131600,"journal":{"name":"2016 11th International Design & Test Symposium (IDT)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125544448","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IDT.2016.7843049
S. Lajnef, N. Boulejfen, F. Ghannouchi
This paper reports a novel band-limited two dimensional (2D) Cartesian behavioral model for concurrent dual-band radio frequency (RF) transmitters. The proposed model is based on using a band-limited technique in order to control the bandwidth of the transmitter. This new approach eliminates the bandwidth requirements in wideband concurrent dual-band transmitters in the presence of in-phase/quadrature (I/Q) modulator imperfections. In order to validate this idea, a broadband class AB PA driven concurrently by two independent LTE signals. The results prove that this approach has significant advantage when modeling the band-limited systems.
{"title":"Band-limited 2D Cartesian behavioral modeling of concurrent dual-band RF transmitters","authors":"S. Lajnef, N. Boulejfen, F. Ghannouchi","doi":"10.1109/IDT.2016.7843049","DOIUrl":"https://doi.org/10.1109/IDT.2016.7843049","url":null,"abstract":"This paper reports a novel band-limited two dimensional (2D) Cartesian behavioral model for concurrent dual-band radio frequency (RF) transmitters. The proposed model is based on using a band-limited technique in order to control the bandwidth of the transmitter. This new approach eliminates the bandwidth requirements in wideband concurrent dual-band transmitters in the presence of in-phase/quadrature (I/Q) modulator imperfections. In order to validate this idea, a broadband class AB PA driven concurrently by two independent LTE signals. The results prove that this approach has significant advantage when modeling the band-limited systems.","PeriodicalId":131600,"journal":{"name":"2016 11th International Design & Test Symposium (IDT)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129680827","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IDT.2016.7843053
H. Abdelali, R. Bedira, H. Trabelsi, A. Gharsallah
This paper describes a novel structure of substrate integrated waveguide (SIW) antenna. The proposed structure is an SIW square cavity backed circular slot antenna. This paper-based SIW antenna has a linear polarization showing enhanced gain and improved bandwidth comparing to previous paper-based SIW antennas. This antenna operates in Ultra wide band (UWB) frequencies and resonates at 5GHz. The eco-friendly materials used in this work with shielded, compact and easy integration in microwave circuit properties combined with the feasibility to be manufactured with low cost fabrication process leads to develop efficiently, wireless communications systems performances. This antenna is useful in Wireless Sensor Network nodes applications as well as for on body-use.
{"title":"Enhanced performances of paper-based Substrate Integrated waveguide (SIW) antenna for Wireless Sensor Network applications","authors":"H. Abdelali, R. Bedira, H. Trabelsi, A. Gharsallah","doi":"10.1109/IDT.2016.7843053","DOIUrl":"https://doi.org/10.1109/IDT.2016.7843053","url":null,"abstract":"This paper describes a novel structure of substrate integrated waveguide (SIW) antenna. The proposed structure is an SIW square cavity backed circular slot antenna. This paper-based SIW antenna has a linear polarization showing enhanced gain and improved bandwidth comparing to previous paper-based SIW antennas. This antenna operates in Ultra wide band (UWB) frequencies and resonates at 5GHz. The eco-friendly materials used in this work with shielded, compact and easy integration in microwave circuit properties combined with the feasibility to be manufactured with low cost fabrication process leads to develop efficiently, wireless communications systems performances. This antenna is useful in Wireless Sensor Network nodes applications as well as for on body-use.","PeriodicalId":131600,"journal":{"name":"2016 11th International Design & Test Symposium (IDT)","volume":"2016 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121405388","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IDT.2016.7843054
Karima Rabaani, N. Boulejfen
Substrate Integrated Waveguide (SIW) is a rectangular waveguide (RWG) with two periodic cylinder side walls (via holes) instead of solid metallic walls. Recently SIW technology became very attractive as it combines the easy integration of the planar technologies with the low loss property of the RWG. In this paper, we are interested in the assessment of the characteristic impedance and the propagation constant of an SIW transmission line. Particularly, a comparative study between the analytical determination of these parameters and their estimation using electromagnetic (EM) finite element based simulations is presented.
{"title":"Characteristic impedance and propagation constant assessment of Substrate Integrated Waveguide transmission line","authors":"Karima Rabaani, N. Boulejfen","doi":"10.1109/IDT.2016.7843054","DOIUrl":"https://doi.org/10.1109/IDT.2016.7843054","url":null,"abstract":"Substrate Integrated Waveguide (SIW) is a rectangular waveguide (RWG) with two periodic cylinder side walls (via holes) instead of solid metallic walls. Recently SIW technology became very attractive as it combines the easy integration of the planar technologies with the low loss property of the RWG. In this paper, we are interested in the assessment of the characteristic impedance and the propagation constant of an SIW transmission line. Particularly, a comparative study between the analytical determination of these parameters and their estimation using electromagnetic (EM) finite element based simulations is presented.","PeriodicalId":131600,"journal":{"name":"2016 11th International Design & Test Symposium (IDT)","volume":"219 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124333551","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IDT.2016.7843031
Khouloud Bouaziz, S. Chtourou, Z. Marrakchi, A. Obeid, M. Abid
Hierarchical representation can greatly simplify many FPGA Computer-Aided Design (CAD) operations such as: design verification, partitioning and placement. In this paper, we propose a hierarchical synthesis environment for Mesh-based FPGA architectures. Our proposed approach uses the flattened netlist resulting from ODIN II tool and reconstructs the hierarchy of the initial Verilog design according to instances names. Results show that reconstructing design hierarchy enables to reduce the number of external nets compared with flattened netlist.
{"title":"Rebuilding synthesized design hierarchy based on instances path names of flattened netlist","authors":"Khouloud Bouaziz, S. Chtourou, Z. Marrakchi, A. Obeid, M. Abid","doi":"10.1109/IDT.2016.7843031","DOIUrl":"https://doi.org/10.1109/IDT.2016.7843031","url":null,"abstract":"Hierarchical representation can greatly simplify many FPGA Computer-Aided Design (CAD) operations such as: design verification, partitioning and placement. In this paper, we propose a hierarchical synthesis environment for Mesh-based FPGA architectures. Our proposed approach uses the flattened netlist resulting from ODIN II tool and reconstructs the hierarchy of the initial Verilog design according to instances names. Results show that reconstructing design hierarchy enables to reduce the number of external nets compared with flattened netlist.","PeriodicalId":131600,"journal":{"name":"2016 11th International Design & Test Symposium (IDT)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123437691","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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