AMS Test Vector Generation using AMS Verification and IEEE P1687.2

Abstract

This paper presents a powerful combination of Analog Mixed-Signal (AMS) verification in combination with emerging IEEE P1687.2 standard, capable of enabling automation of the large part of test pattern generation flow from the specification to Automatic Test Equipment (ATE). The inherent property of AMS verification to incorporate UVM based environment and a configuration with design modules described at arbitrary abstraction levels allows efficient pre-silicon test setup simulation. UVM also facilitates automated generation of STIL, used as the main vehicle to trigger various ATE instruments. The approach is piloted on a power amplifier product that contains BigA and not-so-small D portion. To the best of our knowledge, this is the first proposed self-containing flow that achieves test development reduction and provides guidance for test quality improvement while relying entirely on emerging and existing IEEE standards.