Fully programmable valve arrays (FPVAs) have emerged as a new technology commonly used for biochemical applications. FPVAs have the programmability to perform any bioassay as long as users obtain the fluidic-level synthesis results to configure the fluid loading. Users can purchase a bioassay and the corresponding synthesis result from any bioassay provider. However, the distributed design stages are vulnerable to security threats. Trojans are the most critical threats since they can be inserted in any design stage. Even worse, Trojans would not result in a significant deviation from the original synthesis results, while they can affect the bioassay execution dramatically. In this paper, we propose the six Trojan models for FPVAs and a systematic method for Trojan insertion. In the experiments, we insert Trojans into ten test cases. Most of the Trojan-inserted synthesis results are similar to Trojan-free ones in terms of the efficiency metrics. In other words, the experimental results show that the proposed Trojans for FPVAs are stealthy.
{"title":"Trojan Insertions of Fully Programmable Valve Arrays","authors":"Nadun Sinhabahu, Jian-De Li, Katherine Shu-Min Li, Sying-Jyan Wang, Tsung-Yi Ho","doi":"10.1109/ETS54262.2022.9810384","DOIUrl":"https://doi.org/10.1109/ETS54262.2022.9810384","url":null,"abstract":"Fully programmable valve arrays (FPVAs) have emerged as a new technology commonly used for biochemical applications. FPVAs have the programmability to perform any bioassay as long as users obtain the fluidic-level synthesis results to configure the fluid loading. Users can purchase a bioassay and the corresponding synthesis result from any bioassay provider. However, the distributed design stages are vulnerable to security threats. Trojans are the most critical threats since they can be inserted in any design stage. Even worse, Trojans would not result in a significant deviation from the original synthesis results, while they can affect the bioassay execution dramatically. In this paper, we propose the six Trojan models for FPVAs and a systematic method for Trojan insertion. In the experiments, we insert Trojans into ten test cases. Most of the Trojan-inserted synthesis results are similar to Trojan-free ones in terms of the efficiency metrics. In other words, the experimental results show that the proposed Trojans for FPVAs are stealthy.","PeriodicalId":334931,"journal":{"name":"2022 IEEE European Test Symposium (ETS)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115830819","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-23DOI: 10.1109/ETS54262.2022.9810416
H. Amrouch, K. Chakrabarty, D. Pflüger, I. Polian, M. Sauer, M. Reorda
Recent breakthroughs in machine learning (ML) technology are shifting the boundaries of what is technologically possible in several areas of Computer Science and Engineering. This paper discusses ML in the context of test-related activities, including fault diagnosis, post-silicon validation and yield optimization. ML is by now an established scientific discipline, and a large number of successful ML techniques have been developed over the years. This paper focuses on how to adapt ML approaches that were originally developed with other applications in mind to test-related problems. We consider two specific applications of learning in more depth: delay fault diagnosis in three-dimensional integrated circuits and tuning performed during post-silicon validation. Moreover, we examine the emerging concept of brain-inspired hyperdimensional computing (HDC) and its potential for addressing test and reliability questions. Finally, we show how to integrate ML into actual industrial test and yield-optimization flows.
{"title":"Machine Learning for Test, Diagnosis, Post-Silicon Validation and Yield Optimization","authors":"H. Amrouch, K. Chakrabarty, D. Pflüger, I. Polian, M. Sauer, M. Reorda","doi":"10.1109/ETS54262.2022.9810416","DOIUrl":"https://doi.org/10.1109/ETS54262.2022.9810416","url":null,"abstract":"Recent breakthroughs in machine learning (ML) technology are shifting the boundaries of what is technologically possible in several areas of Computer Science and Engineering. This paper discusses ML in the context of test-related activities, including fault diagnosis, post-silicon validation and yield optimization. ML is by now an established scientific discipline, and a large number of successful ML techniques have been developed over the years. This paper focuses on how to adapt ML approaches that were originally developed with other applications in mind to test-related problems. We consider two specific applications of learning in more depth: delay fault diagnosis in three-dimensional integrated circuits and tuning performed during post-silicon validation. Moreover, we examine the emerging concept of brain-inspired hyperdimensional computing (HDC) and its potential for addressing test and reliability questions. Finally, we show how to integrate ML into actual industrial test and yield-optimization flows.","PeriodicalId":334931,"journal":{"name":"2022 IEEE European Test Symposium (ETS)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116770904","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-23DOI: 10.1109/ETS54262.2022.9810391
Abraham Steenhoek, Praise O. Farayola, Isaac Bruce, Shravan K. Chaganti, Abalhassan Sheikh, S. Ravi, Degang Chen
This paper describes a low-cost technique for extracting parameters of interest for test boards used in multisite automatic test equipment (ATE). In the proposed approach, physical elements and nets on the PCB are represented as a graph with nodes and edges. Graph traversal algorithms are then used to extract data about the connections between specific components on each test site. This approach automates the previously slow and manual process of generating the topology files necessary to extract board parameters. The proposed method is implemented on a multisite test board, and results are presented.
{"title":"Graph Theory Approach for Multi-site ATE Board Parameter Extraction","authors":"Abraham Steenhoek, Praise O. Farayola, Isaac Bruce, Shravan K. Chaganti, Abalhassan Sheikh, S. Ravi, Degang Chen","doi":"10.1109/ETS54262.2022.9810391","DOIUrl":"https://doi.org/10.1109/ETS54262.2022.9810391","url":null,"abstract":"This paper describes a low-cost technique for extracting parameters of interest for test boards used in multisite automatic test equipment (ATE). In the proposed approach, physical elements and nets on the PCB are represented as a graph with nodes and edges. Graph traversal algorithms are then used to extract data about the connections between specific components on each test site. This approach automates the previously slow and manual process of generating the topology files necessary to extract board parameters. The proposed method is implemented on a multisite test board, and results are presented.","PeriodicalId":334931,"journal":{"name":"2022 IEEE European Test Symposium (ETS)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123811448","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-23DOI: 10.1109/ets54262.2022.9810430
Over that last 3 decades, we have witnessed a transition from closed software ecosystems being the foundation for HPC, enterprise, and business to open source software ecosystems based on Linux: from Arduino in the IoT space, to Android in the mobile space to Linux in HPC and cloud-based systems with various Open Source Software projects built on top. However, when examining hardware, current commercial off the shelf solutions are closed hardware ecosystems that only enable integration at the peripheral (PCIe) level. The combination of current technology trends, the slowing of Moore’s Law, and cost prohibitive silicon manufacturing inhibit significant power-performance gains by relying on traditional closed ecosystems, especially in HPC, technology pushed to the extreme. This new regime forces systems to be much more specialized to achieve the power-performance profiles required for a supercomputer. In the past, HPC has led the way forward, defining the bleeding edge of technology. HPC can do this again with open hardware, as it has done in software with adopting Linux and open source in general. This is not only a technology imperative, but one born out of current geopolitics. Digital Technology (the generation and processing of data) is the basis for global commerce, scientific discovery, and ubiquitous in modern life. Thus, creation of digital technology in the form of processors, accelerators and the related digital infrastructure guarantees access to these building blocks of the digital economy regardless of the geopolitical environment. Given this technology and geopolitical backdrop, we describe how Europe can exploit its resources targeting research and development for technological independence. from performance stack, Abstract Root Cause Analysis (RCA) and Layout Pattern Analysis (LPA) are critical technologies for Diagnosis Driven Yield Learning in designing and manufacturing integrated circuits. Recent advancements of AI technologies can help improving yield learning accuracy and transferring the yield learning experiences from old designs to new designs or from old technologies to the new ones. In this talk, we share our experiences in this research area and discuss the following techniques: Abstract The ever-increasing demands of high-performance visual and accelerated computing has resulted in GPUs becoming some of the most complex ASICs being built today. The last few years have also seen an explosion in demand for unique silicon designs serving varied markets such as gaming, HPC, healthcare, smart cities, robotics and automotive. Process scaling is an important factor of delivering such continuous performance gains over the decades. Some of these designs push the limits of current chip manufacturing technology, growing to 80B transistors and beyond. Furthermore, these new designs are implemented with innovative new methods in physical design and are accelerated to reach the market at a staggering pace. Delivering outgoing quality
{"title":"Supercomputers and European Sovereignty ...","authors":"","doi":"10.1109/ets54262.2022.9810430","DOIUrl":"https://doi.org/10.1109/ets54262.2022.9810430","url":null,"abstract":"Over that last 3 decades, we have witnessed a transition from closed software ecosystems being the foundation for HPC, enterprise, and business to open source software ecosystems based on Linux: from Arduino in the IoT space, to Android in the mobile space to Linux in HPC and cloud-based systems with various Open Source Software projects built on top. However, when examining hardware, current commercial off the shelf solutions are closed hardware ecosystems that only enable integration at the peripheral (PCIe) level. The combination of current technology trends, the slowing of Moore’s Law, and cost prohibitive silicon manufacturing inhibit significant power-performance gains by relying on traditional closed ecosystems, especially in HPC, technology pushed to the extreme. This new regime forces systems to be much more specialized to achieve the power-performance profiles required for a supercomputer. In the past, HPC has led the way forward, defining the bleeding edge of technology. HPC can do this again with open hardware, as it has done in software with adopting Linux and open source in general. This is not only a technology imperative, but one born out of current geopolitics. Digital Technology (the generation and processing of data) is the basis for global commerce, scientific discovery, and ubiquitous in modern life. Thus, creation of digital technology in the form of processors, accelerators and the related digital infrastructure guarantees access to these building blocks of the digital economy regardless of the geopolitical environment. Given this technology and geopolitical backdrop, we describe how Europe can exploit its resources targeting research and development for technological independence. from performance stack, Abstract Root Cause Analysis (RCA) and Layout Pattern Analysis (LPA) are critical technologies for Diagnosis Driven Yield Learning in designing and manufacturing integrated circuits. Recent advancements of AI technologies can help improving yield learning accuracy and transferring the yield learning experiences from old designs to new designs or from old technologies to the new ones. In this talk, we share our experiences in this research area and discuss the following techniques: Abstract The ever-increasing demands of high-performance visual and accelerated computing has resulted in GPUs becoming some of the most complex ASICs being built today. The last few years have also seen an explosion in demand for unique silicon designs serving varied markets such as gaming, HPC, healthcare, smart cities, robotics and automotive. Process scaling is an important factor of delivering such continuous performance gains over the decades. Some of these designs push the limits of current chip manufacturing technology, growing to 80B transistors and beyond. Furthermore, these new designs are implemented with innovative new methods in physical design and are accelerated to reach the market at a staggering pace. Delivering outgoing quality","PeriodicalId":334931,"journal":{"name":"2022 IEEE European Test Symposium (ETS)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123634967","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-23DOI: 10.1109/ETS54262.2022.9810438
Jayeeta Chaudhuri, K. Chakrabarty
Multi-tenant FPGAs are increasingly being used in cloud computing technologies. Users are able to access the FPGA fabric remotely to implement custom accelerators in the cloud. However, sharing FPGA resources by untrusted third-parties can lead to serious security threats. Attackers can configure a portion of the FPGA with a malicious bitstream. Such malicious use of the FPGA fabric may lead to severe voltage fluctuations and eventually crash the FPGA. Attackers can also use side-channel and fault attacks to extract secret information (e.g., secret key of an AES encryption module). We propose a convolutional neural network (CNN)-based defense mechanism to detect malicious circuits that are configured on an FPGA by learning features from the data-series representation of the bitstreams of malicious circuits. We use the classification accuracy, true-positive rate, and false-positive rate metrics to quantify the effectiveness of CNN-based classification of malicious bitstreams. Experimental results on Xilinx FPGAs demonstrate the effectiveness of the proposed method.
{"title":"Detection of Malicious FPGA Bitstreams using CNN-Based Learning*","authors":"Jayeeta Chaudhuri, K. Chakrabarty","doi":"10.1109/ETS54262.2022.9810438","DOIUrl":"https://doi.org/10.1109/ETS54262.2022.9810438","url":null,"abstract":"Multi-tenant FPGAs are increasingly being used in cloud computing technologies. Users are able to access the FPGA fabric remotely to implement custom accelerators in the cloud. However, sharing FPGA resources by untrusted third-parties can lead to serious security threats. Attackers can configure a portion of the FPGA with a malicious bitstream. Such malicious use of the FPGA fabric may lead to severe voltage fluctuations and eventually crash the FPGA. Attackers can also use side-channel and fault attacks to extract secret information (e.g., secret key of an AES encryption module). We propose a convolutional neural network (CNN)-based defense mechanism to detect malicious circuits that are configured on an FPGA by learning features from the data-series representation of the bitstreams of malicious circuits. We use the classification accuracy, true-positive rate, and false-positive rate metrics to quantify the effectiveness of CNN-based classification of malicious bitstreams. Experimental results on Xilinx FPGAs demonstrate the effectiveness of the proposed method.","PeriodicalId":334931,"journal":{"name":"2022 IEEE European Test Symposium (ETS)","volume":"538 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124527144","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-23DOI: 10.1109/ETS54262.2022.9810468
Martha Johanna Sepúlveda, Dominik Winkler
Digital signature is a key security technology for authenticating systems and devices, thus enabling the existence of wide collaborative environments. This is also true for safety-critical systems that are constrained by strict performance requirements. Such applications are usually implemented through Multi-processors System-on-Chip (MPSoC). The dawn of quantum computing represents a threat for current cryptography, including the digital signatures. In order to prepare for such an event, electronic systems must integrate quantum-secure (post-quantum) cryptography. Dilithium is one of the main alternatives for practical implementation of post-quantum signatures. While most of the attention has been given to the security analysis and single-core software implementation, the Dilithium MPSoC exploration for high performance has been neglected. To this end, this work presents two contributions. First, the design and exploration of optimized Dilithium multi-core implementations. Second, the deployment of Dilithium on real life MPSoCs used in automotive applications and operated with a commercial RTOS. Results show that Dilithium can be efficiently implemented and optimized on a multicore architecture, improving the performance up to 48% for key generation, 34% for signature and 42% for verification when compared to single core solutions.
{"title":"Super Acceleration of Dilithium in MPSoCs Critical Environments","authors":"Martha Johanna Sepúlveda, Dominik Winkler","doi":"10.1109/ETS54262.2022.9810468","DOIUrl":"https://doi.org/10.1109/ETS54262.2022.9810468","url":null,"abstract":"Digital signature is a key security technology for authenticating systems and devices, thus enabling the existence of wide collaborative environments. This is also true for safety-critical systems that are constrained by strict performance requirements. Such applications are usually implemented through Multi-processors System-on-Chip (MPSoC). The dawn of quantum computing represents a threat for current cryptography, including the digital signatures. In order to prepare for such an event, electronic systems must integrate quantum-secure (post-quantum) cryptography. Dilithium is one of the main alternatives for practical implementation of post-quantum signatures. While most of the attention has been given to the security analysis and single-core software implementation, the Dilithium MPSoC exploration for high performance has been neglected. To this end, this work presents two contributions. First, the design and exploration of optimized Dilithium multi-core implementations. Second, the deployment of Dilithium on real life MPSoCs used in automotive applications and operated with a commercial RTOS. Results show that Dilithium can be efficiently implemented and optimized on a multicore architecture, improving the performance up to 48% for key generation, 34% for signature and 42% for verification when compared to single core solutions.","PeriodicalId":334931,"journal":{"name":"2022 IEEE European Test Symposium (ETS)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126294994","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-23DOI: 10.1109/ETS54262.2022.9810422
Soyed Tuhin Ahmed, M. Mayahinia, Michael Hefenbrock, Christopher Münch, M. Tahoori
Neural Networks (NN) can be efficiently accelerated using emerging resistive non-volatile memories (eNVM), such as Spin Transfer Torque Magnetic RAM(STT-MRAM). However, process variations and runtime temperature fluctuations can lead to miss-quantizing the sensed state and in turn, degradation of inference accuracy. We propose a design-time reference current generation method to improve the robustness of the implemented NN under different thermal and process variation scenarios with no additional runtime hardware overhead compared to existing solutions.
{"title":"Process and Runtime Variation Robustness for Spintronic-Based Neuromorphic Fabric","authors":"Soyed Tuhin Ahmed, M. Mayahinia, Michael Hefenbrock, Christopher Münch, M. Tahoori","doi":"10.1109/ETS54262.2022.9810422","DOIUrl":"https://doi.org/10.1109/ETS54262.2022.9810422","url":null,"abstract":"Neural Networks (NN) can be efficiently accelerated using emerging resistive non-volatile memories (eNVM), such as Spin Transfer Torque Magnetic RAM(STT-MRAM). However, process variations and runtime temperature fluctuations can lead to miss-quantizing the sensed state and in turn, degradation of inference accuracy. We propose a design-time reference current generation method to improve the robustness of the implemented NN under different thermal and process variation scenarios with no additional runtime hardware overhead compared to existing solutions.","PeriodicalId":334931,"journal":{"name":"2022 IEEE European Test Symposium (ETS)","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117273015","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-23DOI: 10.1109/ets54262.2022.9810462
{"title":"ETS 2022 Steering and Program Committees","authors":"","doi":"10.1109/ets54262.2022.9810462","DOIUrl":"https://doi.org/10.1109/ets54262.2022.9810462","url":null,"abstract":"","PeriodicalId":334931,"journal":{"name":"2022 IEEE European Test Symposium (ETS)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129685499","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-23DOI: 10.1109/ETS54262.2022.9810401
Mohamed Thouabtia, A. Oleszczuk, T. Girg, Martin Allinger
Common Mode Transient Immunity (CMTI) is one of the most important key parameters of an isolator. CMTI describes the ability of an isolation barrier to withstand fast common mode transients applied between two isolated circuits and thus to maintain the system integrity. To measure the CMTI, very fast voltage changes between the two isolated circuit grounds must be generated. This paper presents a novel method to generate the transients and measure the CMTI. A DC-DC converter is used with a high voltage switch in addition to an appropriate regulation circuit using only passive elements to generate the desired voltage level and slope. The method was implemented on an evaluation board to evaluate a few commercial digital isolators. Measurement results are presented and discussed.
{"title":"Novel Method to Measure Common Mode Transient Immunity of Isolators","authors":"Mohamed Thouabtia, A. Oleszczuk, T. Girg, Martin Allinger","doi":"10.1109/ETS54262.2022.9810401","DOIUrl":"https://doi.org/10.1109/ETS54262.2022.9810401","url":null,"abstract":"Common Mode Transient Immunity (CMTI) is one of the most important key parameters of an isolator. CMTI describes the ability of an isolation barrier to withstand fast common mode transients applied between two isolated circuits and thus to maintain the system integrity. To measure the CMTI, very fast voltage changes between the two isolated circuit grounds must be generated. This paper presents a novel method to generate the transients and measure the CMTI. A DC-DC converter is used with a high voltage switch in addition to an appropriate regulation circuit using only passive elements to generate the desired voltage level and slope. The method was implemented on an evaluation board to evaluate a few commercial digital isolators. Measurement results are presented and discussed.","PeriodicalId":334931,"journal":{"name":"2022 IEEE European Test Symposium (ETS)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121532948","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-23DOI: 10.1109/ETS54262.2022.9810382
T. Kilian, Markus Hanel, Daniel Tille, M. Huch, Ulf Schlichtmann
Automotive Microcontrollers (MCUs) are extensively tested to guarantee zero-defect quality. Performance screening is one of the critical factors to ensure that MCUs meet quality requirements. Ring Oscillator (RO) structures are used for this performance screening. Such RO structures usually cause routing overhead on the chip. The routing overhead increases, especially when many ROs are implemented. This paper presents a novel self-enabling technique that significantly reduces the routing overhead for functional path ROs. We present a proof of concept on a large automotive MCU. The routing overhead can be reduced by over 80% compared to traditional approaches.
{"title":"Reducing Routing Overhead by Self-Enabling Functional Path Ring Oscillators","authors":"T. Kilian, Markus Hanel, Daniel Tille, M. Huch, Ulf Schlichtmann","doi":"10.1109/ETS54262.2022.9810382","DOIUrl":"https://doi.org/10.1109/ETS54262.2022.9810382","url":null,"abstract":"Automotive Microcontrollers (MCUs) are extensively tested to guarantee zero-defect quality. Performance screening is one of the critical factors to ensure that MCUs meet quality requirements. Ring Oscillator (RO) structures are used for this performance screening. Such RO structures usually cause routing overhead on the chip. The routing overhead increases, especially when many ROs are implemented. This paper presents a novel self-enabling technique that significantly reduces the routing overhead for functional path ROs. We present a proof of concept on a large automotive MCU. The routing overhead can be reduced by over 80% compared to traditional approaches.","PeriodicalId":334931,"journal":{"name":"2022 IEEE European Test Symposium (ETS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125189360","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：