Power Distribution Network Optimization for On-Die Regulator with Laplace Transform Technique

Abstract

This paper introduces a methodology to co-design on-chip linear dropout regulator (LDO) with power distribution network of package and PCB board based on Laplace transform method. A practical methodology demonstrates the effectiveness and the efficiency of the Laplace model in the time domain and is derived that takes into account LDO-PDN system impedance response. LDO pass transistor size and output decoupling capacitor optimization flow is proposed to meet the system voltage noise requirements. The goal is to provide sufficient performance for efficient system solutions in the early stages of design and achieve success at the system level.